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CDCD5704PWRG4 Fiches technique(PDF) 8 Page - Texas Instruments

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No de pièce CDCD5704PWRG4
Description  Rambus XDR CLOCK GENERATOR
Download  19 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

CDCD5704PWRG4 Fiches technique(HTML) 8 Page - Texas Instruments

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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
CDCD5704
SCAS823 – DECEMBER 2006
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
UNIT
VDD
Supply voltage range
–0.3 to 2.8
V
For SCL and SDA
–0.3 to 3.6
VI
Input voltage range (2)
V
For all other inputs
–0.3 to VDD + 0.25
VO
Output voltage range (2)
–0.5 to VDD + 0.5
V
IIK
Input clamp current, (VI < 0, VI > VDD)
±20
mA
IO
Continuous output current
±50
mA
No airflow
94.4
Airflow 150 ft/min
82.8
RθJA Thermal resistance, junction-to-ambient
(3)
K/W
Airflow 250 ft/min
79.1
Airflow 500 ft/min
74
RθJC Thermal resistance, junction-to-case
(3)
No airflow
31.8
K/W
RθJB Thermal resistance, junction-to-board
(3)
No airflow
68.9
K/W
TJ
Maximum junction temperature
125
°C
Tstg
Storage temperature range
–65 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3)
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S1P (high-k board).
MIN
NOM
MAX
UNIT
VDDP
Supply voltage for PLL
2.375
2.5
2.625
V
VDDC
Supply voltage for core
2.375
2.5
2.625
V
VDD
Supply voltage for clock buffers
2.375
2.5
2.625
V
TA
Operating free-air temperature
0
70
°C
VIL,CLK
Low-level input voltage, REFCLK/REFCLKB
–0.15
0.15
V
VIX,CLK
Crossing-point voltage, input voltage threshold, REFCLK/REFCLKB
0.2
0.55
V
VIH,CLKD
High-level input voltage, REFCLK/REFCLKB
0.6
0.95
V
∆V
IX,CLK
Difference in crossing-point voltage
0.15
V
VIL SE
Low-level, single-ended input voltage, REFCLK
–0.15
Vth SE – 0.3
V
Vth SE
Single-ended input-voltage threshold, REFCLK (1)
0.35
0.5 VDD
V
VIH SE
High-level, single-ended input voltage, REFCLK
Vth SE + 0.3
2.625
V
VIL L
Low-level input voltage, ID0, ID1, EN, BYPASS
–0.15
0.8
V
VIH L
High-level input voltage, ID0, ID1, EN, BYPASS
1.4
2.625
V
VIL SM
Low-level input voltage, SCL, SDA (2)
–0.15
0.8
V
VIH SM
High-level input voltage, SCL, SDA (2)
1.4
3.465
V
(1)
When using a single-ended clock input, Vth is supplied to the REFCLKB pin. Duty cycle of single-ended REFCLK input is measured at
Vth.
(2)
This range of SCL and SDA input high voltage allows the CDCD5704 to co-exist with 3.3 V, 2.5 V, and 1.8 V devices on the same
serial-interface bus system.
8
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