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CDCD5704PW Fiches technique(PDF) 10 Page - Texas Instruments |
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CDCD5704PW Fiches technique(HTML) 10 Page - Texas Instruments |
10 / 19 page www.ti.com CDCD5704 SCAS823 – DECEMBER 2006 DEVICE CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOL/IREF Ratio of output low current to reference current 6.8 7 7.2 IOL,ABS Minimum current at VOL,ABS(5) VOL,ABS = 0.85 V 45 mA VDD = 2.375 V to 2.625 V, VOL,SDA SDA output low voltage 0.4 V IOH = 4 mA VDD = 2.375 V to 2.625 V, IOL,SDA SDA output low current 6 mA VO = 0.8 V IOZ Output 3-state current CLK0 to CLK4 ±50 µA IIR REFCLK input current VI = 0 V or VDD ±5 µA IIL Logic input current VI = 0 V or VDD ±10 µA AC DEVICE CHARACTERISTICS Input capacitance, REFCLK, CIR 2 7 pF REFCLKB (6) CIL Input capacitance logic pins(7) 2 10 pF 300 MHz to 667 MHz, possible tCYCLE Clock cycle time (8) 1.5 3.33 ns SSC is not taken into account 10,000 cycles, 300 MHz 40 to 635 MHz(9) tjit(per) |Cycle-to-cycle jitter| of 1–6 clock cycles ps 10,000 cycles, 636 MHz 30 to 667 MHz(9) L1 SSB phase noise at 1 MHz 300-MHz–667-MHz output (10) –115 –97 dBc/Hz L20 SSB phase noise at 20 MHz 300-MHz–667-MHz output(10) –150 –128 dBc/Hz VDD = 2.375 V to 2.625 V, ∆t skew(o) Drift in tskew(o)(11) 15 ps T = 0 to 70 °C odc Output duty cycle 45% 50% 55% 300 MHz to 635 MHz 40 tODC,ERR |Cycle-to-cycle| duty-cycle error ps 636 MHz to 667 MHz 30 tERR,SSC PLL output phase error when tracking SSC –100 100 ps tr/tf Output rise and fall time VOUT = 20%–80% 100 300 ps VOUT = 20%–80%, fout = 300 MHz tcr/tcf Difference between output rise and fall times 100 ps to 667 MHz ZOUT Output dynamic impedance(12) VOL = 0.9 V 750 Ω Time from VDD, VDDP, VDDC tL Power-up lock time being applied and settled until 3 ms clock outputs are settled PLL lock time after (1) frequency change via Time from signals for selecting a serial interface (programming of SCL and SDA mode of operation (1) or (2) tL(ω) 3 ms pins completed) or (2) EN and/or BYPASS applied and settled until clock changed state outputs are settled (5) Minimum IOL,ABS is measured at the clock output pins of the package, as shown in Figure 3. (6) Capacitance measured at frequency = 1 MHz, dc bias = 0.9 V, and VAC < 100 mV (7) Capacitance measured at frequency = 1 MHz, dc bias = 0.9 V, and VAC < 100 mV (8) Maximum and minimum output clock cycle times are based on nominal output frequency of 300 MHz and 667 MHz, respectively. For spread-spectrum-modulated differential or single-ended REFCLK, the output clock tracks the modulation of the input. (9) Output short-term jitter specification is the absolute value of the worst-case deviation and is defined in the Jitter section. (10) Device must not exceed the upper limit of L(f) for 1-MHz to 100-MHz offset as shown in the Phase Noise section. (11) tskew is the timing difference between any two of the four differential clocks and is measured at common-mode voltage. ∆tskew is the change in tskew when the operating temperature and supply voltage change. (12) ZOUT is defined at the output pins directly. The value is determined as the ac small-signal impedance at low frequencies (< 100 kHz) and when output is driving a high state. 10 Submit Documentation Feedback |
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