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ADS6425 Fiches technique(PDF) 1 Page - Texas Instruments

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No de pièce ADS6425
Description  QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

ADS6425 Fiches technique(HTML) 1 Page - Texas Instruments

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FEATURES
APPLICATIONS
DESCRIPTION
ADS6425
SLWS197 – MARCH 2007
QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE
• Base-station IF Receivers
• Maximum Sample Rate: 125 MSPS
• Diversity Receivers
• 12-Bit Resolution with No Missing Codes
• Medical Imaging
• 1.65-W Total Power
• Test Equipment
• Simultaneous Sample and Hold
• 70.3 dBFS SNR at Fin = 50 MHz
• 83 dBc SFDR at Fin = 50 MHz, 0 dB Gain
The
ADS6425
is
a
high
performance
12-bit,
• 79 dBc SFDR at Fin = 170 MHz, 3.5 dB Gain
125-MSPS quad channel ADC. Serial LVDS data
• 3.5 dB Coarse Gain and up to 6 dB
outputs
reduce
the
number
of
interface
lines,
Programmable Fine Gain for SFDR/SNR
resulting in a compact 64-pin QFN package (9 mm
×
9 mm) that allows for high system integration density.
Trade-Off
The device includes 3.5 dB coarse gain option that
• Serialized LVDS Outputs with Programmable
can be used to improve SFDR performance with little
Internal Termination Option
degradation in SNR. In addition to the coarse gain,
• Supports Sine, LVCMOS, LVPECL, LVDS
fine gain options also exist, programmable in 1dB
Clock Inputs and Amplitude Down to 400 mVpp
steps up to 6dB.
differential
The output interface is 2-wire, where each ADC's
• Internal Reference with External Reference
data is serialized and output over two LVDS pairs.
Support
This makes it possible to halve the serial data rate
(compared to a 1-wire interface) and restrict it to less
• No External Decoupling Required for
than 1Gbps easing receiver design. The ADS6425
References
also includes the traditional 1-wire interface that can
• 3.3-V Analog and Digital Supply
be used at lower sampling frequencies.
• 64 QFN Package (9 mm × 9 mm)
An internal phase locked loop (PLL) multiplies the
• Pin Compatible 14-Bit Family (ADS644X)
incoming ADC sampling clock to derive the bit clock.
The bit clock is used to serialize the 12-bit data from
each channel. In addition to the serial data streams,
the frame and bit clocks are also transmitted as
LVDS outputs. The LVDS output buffers have
features such as programmable LVDS currents,
current doubling modes and internal termination
options. These can be used to widen eye-openings
and improve signal integrity, easing capture by the
receiver.
The ADC channel outputs can be transmitted either
as MSB or LSB first and 2s complement or straight
binary.
ADS6425 has internal references, but can also
support an external reference mode. The device is
specified over the industrial temperature range
(–40
°C to 85°C).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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