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ISL5314 Fiches technique(PDF) 4 Page - Intersil Corporation |
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ISL5314 Fiches technique(HTML) 4 Page - Intersil Corporation |
4 / 16 page 4 where N = 1–5 (for 8–40 bit serial data) and fCLK is the DDS clock rate. Three extra SCLKs are required (one for the SYNC pulse plus two additional for register transfer). The latency in seconds depends on how many bits of serial data are being written and the speeds of both clocks. The center and offset frequency registers cannot be written using the serial pins. They must be programmed using the parallel interface. In order to use the three wire serial interface in a mode that is not the default mode, the parallel control bus must be used to reprogram register 12. Register 12 can be set according to the desired options of the serial interface that are described in the register description table. Since the serial register defaults enabled, it must be disabled in register 13 (bit 6) if it is not used. Register 14 The parallel control bus must be used to program register 14 with 0x00h or 0x30h after assertion of RESET. See the Control Register table in the back of the datasheet for more information. Control Pins There are three control pins provided for phase and frequency control. The PH0 and PH1 pins select phase offsets of 0, 90, 180, and 270 degrees and can be used for low speed, unfiltered BPSK or QPSK modulation. These pins can also be used for providing sine/cosine when using two ISL5314s together as quadrature local oscillators. The ENOFR pin enables or zeros the offset frequency word to the phase accumulator and can be used for FSK or MSK modulation. These control pins and the UPDATE pin are passed through special cells to minimize the probability of metastability. Writing anything to register 15 behaves like an UPDATE so that the user can save one control pin if desired. Reset A RESET pin is available which resets all registers to their defaults. Register 14 must always be written with 0x00h or 0x30h after a RESET. In order to reset the part, the user must take the RESET pin low, allow at least one CLK rising edge, and then take the RESET pin high again. The latency from the RESET pin going high until the output reflects the reset is eleven CLK cycles. See the register description table in the back of the data sheet for the default states of all bits in all registers. After RESET goes high, one rising edge of CLK is required before the control registers can be written to again. The center frequency register resets to fCLK/4. The offset frequency register resets to an unknown frequency but is disabled. The serial frequency register resets to an unknown frequency and is enabled. If the serial register is not used, disable it in register 13 using the parallel interface. Comparator A comparator is provided for square wave output generation. The user can take the DDS analog output, filter it, and then send it back into the comparator. A square wave will be generated at the comparator output (COMPOUT pin) at an amplitude level that is dependent on the digital power supply (DVDD). The comparator was designed to operate at speeds comparable to the DDS output frequency range (approximately 0–50MHz). It is not intended for low jitter applications (<0.5ns). The comparator has a sleep mode that is activated by connecting both inputs (IN- and IN+) to the analog power supply plane. This will save approximately 4mA of current (as shown in the Typical Application Circuit). If the comparator is not used, leave the COMPOUT pin floating. DAC Voltage Reference The internal voltage reference for the DAC has a nominal value of +1.2V with a ±60ppm/oC drift coefficient over the full temperature range of the converter. It is recommended that a 0.1 µF capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin (11) selects the reference. The internal reference can be selected if pin 11 is tied low (ground). If an external reference is desired, then pin 11 should be tied high (the analog supply voltage) and the external reference driven into REFIO, pin 12. The full-scale output current of the converter is a function of the voltage reference used and the value of RSET. IOUT should be within the 2mA–20mA range, though operation below 2mA is possible, with performance degradation. If the internal reference is used, VFSADJ will equal approximately 1.2V (pin 13). If an external reference is used, VFSADJ will equal the external reference. IOUT(Full Scale) = (VFSADJ/RSET) X 32. TABLE 1. FREQUENCY CONTROL BIT ALIGNMENTS 48 Bits (Individual Bit Alignment) 4444 4444 3333 3333 3322 2222 2222 1111 1111 1100 0000 0000 7654 3210 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210 Phase Accumulator xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Center Frequency xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Offset Frequency xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Serial Frequency, 8 Bits xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Serial Frequency, 16 Bits xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 Serial Frequency, 24 Bits xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 Serial Frequency, 32 Bits xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 Serial Frequency, 40 Bits xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 ISL5314 |
Numéro de pièce similaire - ISL5314_05 |
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Description similaire - ISL5314_05 |
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