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AM50DL128BH56IS Fiches technique(PDF) 10 Page - SPANSION

No de pièce AM50DL128BH56IS
Description  Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories
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AM50DL128BH56IS Fiches technique(HTML) 10 Page - SPANSION

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Am50DL128BH
February 6, 2004
ADV ANCE
I N FO RMAT I O N
PIN DESCRIPTION
A20–A0
= 21 Address Inputs (Common)
A21, A-1
= 2 Address Inputs (Flash)
DQ15–DQ0
= 16 Data Inputs/Outputs (Common)
CE#f1
= Chip Enable 1 (Flash 1)
CE#f2
= Chip Enable 2 (Flash 2)
CE#1s
= Chip Enable 1 (pSRAM)
CE2s
= Chip Enable 2 (pSRAM)
OE#
= Output Enable (Common)
WE#
= Write Enable (Common)
RY/BY#
= Ready/Busy Output
UB#s
= Upper Byte Control (pSRAM)
LB#s
= Lower Byte Control (pSRAM)
CIOf
= I/O Configuration (Flash)
CIOf = V
IH = Word mode (x16),
CIOf = V
IL = Byte mode (x8)
RESET#
= Hardware Reset Pin, Active Low
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
V
CCf
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
V
CCs
= pSRAM Power Supply
V
SS
= Device Ground (Common)
NC
= Pin Not Connected Internally
LOGIC SYMBOL
21
16 or 8
DQ15–DQ0
A20–A0
CE#f1
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
SA
A21, A-1
LB#s
CIOf
CE#1s
CE2s
CE#f2


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