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AM42DL6402G Fiches technique(PDF) 42 Page - SPANSION |
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AM42DL6402G Fiches technique(HTML) 42 Page - SPANSION |
42 / 62 page January 31, 2003 Am42DL6402G 41 P R E L IMINARY FLASH AC CHARACTERISTICS Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 12 and Table 14 for test specifications 3. Measurements performed by placing a 50 Ω termination on the data pin with a bias of V CC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF . Parameter Description Test Setup Speed JEDEC Std. 70 85 Unit tAVAV tRC Read Cycle Time (Note 1) Min 70 85 ns t AVQV t ACC Address to Output Delay CE#f, OE# = V IL Max 7085ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max 7085ns t GLQV t OE Output Enable to Output Delay Max 30 40 ns tEHQZ tDF Chip Enable to Output High Z (Notes 1, 3) Max 30 35 ns t GHQZ t DF Output Enable to Output High Z (Notes 1, 3) Max 16 ns t AXQX t OH Output Hold Time From Addresses, CE#f or OE#, Whichever Occurs First Min 0 ns t OEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns tOH tCE Outputs WE# Addresses CE#f OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH 0 V RY/BY# RESET# tDF Figure 15. Read Operation Timings |
Numéro de pièce similaire - AM42DL6402G |
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Description similaire - AM42DL6402G |
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