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AM42DL1642DB45IT Fiches technique(PDF) 10 Page - Advanced Micro Devices |
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AM42DL1642DB45IT Fiches technique(HTML) 10 Page - Advanced Micro Devices |
10 / 128 page 8 Am42DL16x2D February 6, 2004 PIN DESCRIPTION A0–A16 = 17 Address Inputs (Common) A–1, A19–A17 = 4 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#s = Chip Enable (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (SRAM) LB#s = Lower Byte Control (SRAM) CIOf = I/O Configuration (Flash) CIOf = VIH = Word mode (x16), CIOf = VIL = Byte mode (x8) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) VCCf = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) VCCs = SRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL 17 16 DQ15–DQ0 A16–A0 CE#f OE# WE# RESET# UB#s RY/BY# WP#/ACC A–1, A19–A17 LB#s CIOf CE1#s CE2s |
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