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AM29DL800BB70WBF Fiches technique(PDF) 4 Page - Advanced Micro Devices |
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AM29DL800BB70WBF Fiches technique(HTML) 4 Page - Advanced Micro Devices |
4 / 46 page 2 Am29DL800B 21519C4 December 4, 2006 D A TA SH EET GENERAL DESCRIPTION The Am29DL800B is an 8 Mbit, 3.0 volt-only flash memory device, organized as 524,288 words or 1,048,576 bytes. The device is offered in 44-pin SO, 48-pin TSOP, and 48-ball FBGA packages. The word- wide (x16) data appears on DQ0–DQ15; the byte-wide (x8) data appears on DQ0–DQ7. This device requires only a single 3.0 volt VCC supply to perform read, pro- gram, and erase operations. A standard EPROM programmer can also be used to program and erase the device. This device is manufactured using AMD’s 0.35 µm pro- cess technology, and offers all the features and benefits of the Am29DL800, which was manufactured using a 0.5 µm technology. The standard device offers access times of 70, 90, and 120 ns, allowing high-speed microprocessors to oper- ate without wait states. Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides si- multaneous operation by dividing the memory space into two banks. Bank 1 contains eight boot/parameter sectors, and Bank 2 consists of fourteen larger, code sectors of uniform size. The device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and simultaneously read from the other bank, with zero la- tency. This releases the system from waiting for the completion of program or erase operations. Am29DL800B Features The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command reg- ister using standard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming cir- cuitry. Write cycles also internally latch addresses and data needed for the programming and erase opera- tions. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase com- mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protec- tion feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector within that bank that is not selected for erasure. True background erase can thus be achieved. There is no need to suspend the erase operation if the read data is in the other bank. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device to reading array data, enabling the sys- tem microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the high est leve ls of qua lity, reliability, an d cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte or word at a time using hot electron injection. |
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