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SN74ALVCH16373 Fiches technique(PDF) 1 Page - Texas Instruments

No de pièce SN74ALVCH16373
Description  16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
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SN74ALVCH16373 Fiches technique(HTML) 1 Page - Texas Instruments

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SN74ALVCH16373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES020F – JULY 1995 – REVISED MAY 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus
 Family
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
description
This 16-bit transparent D-type latch is designed
for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16373 is particularly suitable for
implementing
buffer
registers,
I/O
ports,
bidirectional bus drivers, and working registers.
This device can be used as two 8-bit latches or
one 16-bit latch. When the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state
(high
or
low
logic
levels)
or
the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not affect internal operations of the latch. Old data
can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SSOP
DL
Tube
SN74ALVCH16373DL
ALVCH16373
40
°Cto85°C
SSOP – DL
Tape and reel
SN74ALVCH16373DLR
ALVCH16373
–40
°C to 85°C
TSSOP – DGG
Tape and reel
SN74ALVCH16373DGGR
ALVCH16373
VFBGA – GQL
Tape and reel
SN74ALVCH16373KR
VH373
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
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48
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1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.


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