AD7545JN datasheet(2/8 Pages) INTERSIL

No de pièce	AD7545JN

Description	12-Bit, Buffered, Multiplying CMOS DAC

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Fabricant	INTERSIL [Intersil Corporation]

Site Internet	http://www.intersil.com/cda/home

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Absolute Maximum Ratings

Thermal Information

Supply Voltage (VDD to DGND).. .. .. .. .. .. .. .. . . . -0.3V,+17V

Digital Input Voltage to DGND . .. .. .. .. .. .. .. . -0.3V,VDD +0.3V

VRFB,VREF to DGND . ... .. .. .. .. .. .. .. .. .. ... .. .. .. ±25V

VPIN1 to DGND .. .. .. ... .. .. .. .. .. .. .. .. .. -0.3V, VDD +0.3V

AGND to DGND .. .. .. ... .. .. .. .. .. .. .. .. .. -0.3V, VDD +0.3V

Operating Conditions

Temperature Range .. ... .. .. .. .. .. .. .. .. .. ... . 0oCto 70oC

Thermal Resistance (Typical, Note 1)

θJA (oC/W)

PDIP Package . . . . . . ... .. .. .. .. .. .. .. .. .. ..

80

Maximum Junction Temperature (PDIP Package) . . . . . . . . . 150oC

Maximum Storage Temperature Range .. .. .. .. .. -65oCto 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationof the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1.

θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications

TA = See Note 2, VREF =+10V, VOUT1 = 0V, AGND = DGND, Unless Otherwise Specified

PARAMETER

TEST CONDITIONS

VDD =+5V (NOTE 7)

VDD =+15V (NOTE 7)

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

STATIC PERFORMANCE

Resolution

12

-

12

-

Bits

Relative Accuracy

J

-

±2-

-

±2LSB

K-

-

±1-

-

±1LSB

Differential Nonlinearity

J

10-Bit Monotonic TMIN to TMAX

--

±4-

-

±4LSB

K

12-Bit Monotonic TMIN to TMAX

--

±1-

-

±1LSB

Gain Error

(Using Internal RFB)

J

DAC Register Loaded with

1111 1111 1111

--

±20

-

±25

LSB

K

Gain Error is Adjustable

Using the Circuits of

Figures 5 and 6 (Note 3)

--

±10

-

±15

LSB

Gain Temperature Coefficient

∆Gain/∆Temperature

Typical Value is 2ppm/oCfor

VDD =+5V (Note 4)

--

±5-

-

±10

ppm/oC

DC Supply Rejection

∆Gain/∆VDD

∆VDD = ±5%

0.015

-

0.03

0.01

-

0.02

%

Output Leakage Current at

OUT1

J, K

DB0 - DB11 = 0V; WR,

CS =0V (Note 2)

-

50

-

50

nA

DYNAMIC CHARACTERISTICS

Current Settling Time

To 1/2 LSB, OUT1 LOAD = 100Ω,

DAC Output Measured from Falling

Edge of WR,CS =0V (Note 4)

--

2

-

2

µs

Propagation Delay from Digital Input

Change to 90% of Final Analog Output

OUT1 LOAD = 100

Ω,

CEXT =13pF(Notes 4 and5)

-

300

-

250

ns

Digital to Analog Glitch Impulse

VREF =AGND

-

400

-

250

-

nV/s

AC Feedthrough at OUT1

VREF = ±10V, 10kHz Sinewave

-

5

-

5

-

mVP-P

ANALOG OUTPUTS

Output Capacitance

COUT1 DB0 - DB11 = 0V,

WR,CS =0V (Note 4)

-

70

-

70

pF

DB0 - DB11 = VDD,

WR,CS =0V (Note 4)

-

200

-

200

pF

AD7545

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