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CS82C50A-5Z Fiches technique(PDF) 5 Page - Intersil Corporation |
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CS82C50A-5Z Fiches technique(HTML) 5 Page - Intersil Corporation |
5 / 25 page 5 FN2958.5 August 24, 2006 82C50A OUT1 34 O L OUTPUT 1: This is a general purpose output that can be programmed ACTIVE (low) by settingVCR(2) (OUT1) of the Modem Control Register to a high level. The OUT1 pin is set high by Master Reset. The OUT1 pin is INACTIVE (high) during loop mode operation. OUT2 31 O L OUTPUT 2: This is a general purpose output that can be programmed ACTIVE (low) by setting MCR(3) (OUT1) of the Modem Control Register to a high level. The OUT2 pin is set high by Master Reset. The OUT2 signal is INACTIVE (high) during loop mode operation. RI 39 1 L RING INDICATOR: When low, RI indicates that a telephone ringing signal has been received by the modem or data set. The RI signal is a modem control input whose condition is tested by reading MSR(6) (RI). The Modem Status Register output TERI (MSR(2)) indicates whether the RI input has changed from a Low to High since the previous reading of the MSR. If the interrupt is enabled (IER (3) = 1) and RI changes from a Low to High, an interrupt is generated. The ACTIVE (low) state of RI indicates that the DCE is receiving a ringing signal. RI will appear ACTIVE for approximately the same length of time as the ACTIVE segment of the ringing cycle. The INACTIVE state of RI will occur during the INACTIVE segments not detected by the DCE. This circuit is not disabled by the INACTIVE condition of DTR. DCD 38 I L DATA CARRIER DETECT: When ACTIVE (low), DCD indicates that the data carrier has been detected by the modem or data set. DCD is a modem input whose condition can be tested by the CPU by reading MSR(7) (DCD) of the Modem Status Register. MSR(3) (DDCD) of the Modem Status Register indicates whether the DCD input has changed since the previous reading of the MSR. DOD has no effect on the receiver. If the DCD changes state with the modem status interrupt enabled, an interrupt is generated. When DCD is ACTIVE (low), the received line signal from the remote terminal is within the limits specified by the DCE manufacturer. The INACTIVE (high) signal indicates that the signal is not within the specified limits, or is not present. MR 35 1 H MASTER RESET: The MR input forces the 82C50A into an idle mode in which all serial data activities are suspended. The Modem Control Register (MCR) along with its associated outputs are cleared. The Line Status Register (LSR) is cleared except for the THRE and TEMT bits, which are set. The 82C50A remains in an idle state until programmed to resume serial data activities. The MR input is a Schmitt trigger input. See the DC Electrical Characteristics for Schmitt trigger logic input voltage levels. See Table 7 for a summary of Master Reset’s effect on 82C50A operation. lNTRPT 30 O H INTERRUPT REQUEST: The lNTRPT output goes ACTIVE (high) when one of the following interrupts has an ACTIVE (high) condition and is enabled by the Interrupt Enable Register: Receiver Error flag, Received Data Available, Transmitter Holding Register Empty, and Modem Status. The lNTRPT is reset low upon appropriate service or a MR operation. See Figure 1. Interrupt Control Structure. SIN 10 I H SERIAL DATA INPUT: The SIN input is the serial data input from the communication line or modem to the 82C50A receiver circuits. A mark (1) is high, and a space (0) is low. Data inputs on SIN are disabled when operating in the loop mode. VCC 40 H VCC: +5V positive power supply pin. A 0.1μA decoupling capacitor from VCC (pin 40) to GND (pin 20) is recommended. CS0, CS1, CS2 12,13, 14 I I H, H, L CHIP SELECT: The Chip Select inputs act as enable signals for the write (DOSTR, DOSTR) and read (DlSTR, DlSTR) input signals. The Chip Select inputs are latched by the ADS input. NC 29 Do Not Connect CSOUT 24 O H CHIP SELECT OUT: When ACTIVE (high), this pin indicates that the chip has been selected by active CS0, CS1, and CS2 inputs. No data transfer can be initiated until CSOUT is a logic 1, ACTIVE (high). DDIS 23 O H DRIVER DISABLE: This output is INACTIVE (low) when the CPU is reading data from the 82C50A. An ACTIVE (high) Dells output can be used to disable an external transceiver when the CPU is reading data. ADS 25 I L ADDRESS STROBE: When ACTIVE (low), ADS latches the Register Select (A0, A1, A2) and Chip Select (CS0, CS1, CS2) inputs. An active ADS is required when the Register Select pins are not stable for the duration of the read or write operation, multiplexed mode. If not required, the ADS input should be tied low, non-multiplexed mode. RCLK 9 I This input is the 16X Baud Rate Clock for the receiver section of the 82C50A. This input may be provided from the BAUDOUT output or an external clock. Pin Description (Continued) SYMBOL PIN NUMBER TYPE ACTIVE LEVEL DESCRIPTION |
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