The BCM94500 advanced modulation satellite receiver

evaluation system is intended for use by satellite systems

engineers for the evaluation of the high performance offered by

the BCM4500 advanced modulation satellite receiver with

turbo code FEC. It is also intended for use by hardware

designers and software developers to reduce product design and

development time.

This evaluation platform provides the ideal environment for

systems engineers to explore the emerging technology enabled

by turbo code FECs and the unparalleled performance offered

by the BCM4500.

The simplified user interface gives

engineers easy access to various system parameters, allowing

them to select optimal settings for the BCM4500 to match the

link budget requirements. Hardware engineers and software

developers can use the BCM94500 as a baseline for the final

product architecture and also use it as a test and measurement

device to verify their final product performance.

The BCM94500 supports QPSK, 8PSK and 16 QAM operation

with turbo code FEC over a range of coding and symbol rates.

legacy system compatibility testing.

The BCM94500 contains the BCM3440 direct conversion

CMOS satellite tuner, which supports the full 950–2150 MHz

operating range. Baseband IQ outputs are connected directly to

the BCM4500 receiver. All tuner AGC loops are controlled by

the BCM4500. The BCM4500 process the I/Q baseband signal

through a variable rate advanced modulation receiver and can

use either the turbo code FEC or legacy DVB-S/

DIRECTV

FEC.

The

MPEG-2,

DIRECTV-

or

DVB-compliant output is available on a 25-pin connector,

driven by line drivers for connection to external test equipment

or for interfacing to the BCM97031 HDTV video/graphics

subsystem for decoding and display. Additional on-board

components are provided as an interface between the

multiple switches.

installation and testing. The host software communicates with

host software contains several screens for chip configuration,

constellation monitoring, and performance monitoring including

SNR, block error calculations and other FEC performance

parameters. Testing is simplified by having the option to use

other external BERTs or the BCM4500 on-chip BERT.

A detailed user manual is provided that describes the host

software interface as well as the operation of the BCM4500

API for embedded host software development. All acquisition

scripts and monitoring calculations are performed in the

BCM4500 internal microcontroller and are transparent to the

host. The BCM94500 package is delivered with the user

manual, schematic drawings, and a bill of materials. PCB

Gerber files are also available.

BCM94500

OVER VIEW

RA_I

RA_Q

A/D

A/D

7

7

Phase/

Frequency

Recovery

Variable

Rate

Demod

Acquisition/Tracking Loops

and Clock Generation

AGC_CTRL

Nyquist

α=0.20,0.35

Nyquist

α=0.20,0.35

12-tap

FFE

Block

Header

Processor

Iterative

Decoder

Outer

RS

Decoder

t=10

M

U

X

Viterbi

Decoder

Sync &

Deinter-

leaver

RS

Decoder

Acquisition

Microcontroller

MBus/SPI

Interface

DATA[7:0]

CLK

VALID

SYNC

ERR

MICRO[4:0]

DiSEqC 2.0

DISEQC

BCM4500 Block Diagram

®

Phone: 949-450-8700

FAX: 949-450-8710

Email: info@broadcom.com

Web: www.broadcom.com

BROADCOM CORPORATION

16215 Alton Parkway, P.O. Box 57013

Irvine, California 92619-7013

© 2003 by BROADCOM CORPORATION. All rights reserved.

94500-PB04-R-06.25.03