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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ATTINY2313-20MU Fiches technique(PDF) 40 Page - ATMEL Corporation |
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ATTINY2313-20MU Fiches technique(HTML) 40 Page - ATMEL Corporation |
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40 / 231 page  40 ATtiny2313/V 2543I–AVR–04/06 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period t TOUT. Refer to page 47 for details on operation of the Watchdog Timer. Figure 19. Watchdog Reset During Operation MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. CK CC Bit 765 432 10 – – – – WDRF BORF EXTRF PORF MCUSR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 See Bit Description |
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Description similaire - ATTINY2313-20MU |
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