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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AT90S2313 Fiches technique(PDF) 22 Page - ATMEL Corporation |
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AT90S2313 Fiches technique(HTML) 22 Page - ATMEL Corporation |
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22 / 92 page  22 AT90S2313 0839I–AVR–06/02 interrupt. Some of the Interrupt Flags can also be cleared by writing a logical “1” to the flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. If one or more interrupt conditions occur when the Global Interrupt Enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set (one), and will be executed by order of priority. Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is active. Note that the Status Register is not automatically stored when entering an interrupt rou- tine and restored when returning from an interrupt routine. This must be handled by software. General Interrupt Mask Register – GIMSK • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corre- sponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also “External Interrupts”. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the External Interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corre- sponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT90S2313 and always read as zero. Bit 7 6 5 4 3 2 1 0 $3B ($5B) INT1 INT0 – – – – – – GIMSK Read/Write R/W R/W R R R R R R Initial value 0 0 0 0 0 0 0 0 |
Numéro de pièce similaire - AT90S2313_02 |
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Description similaire - AT90S2313_02 |
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