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OP177GS Fiches technique(PDF) 4 Page - Analog Devices |
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OP177GS Fiches technique(HTML) 4 Page - Analog Devices |
4 / 16 page OP177 Rev. E | Page 4 of 16 @ VS = ±15 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted. Table 2. OP177F OP177G Parameter Symbol Conditions Min Typ Max Min Typ Max Unit INPUT Input Offset Voltage VOS 15 40 20 100 μV Average Input Offset Voltage Drift1 TCVOS 0.1 0.3 0.7 1.2 μV/°C Input Offset Current IOS 0.5 2.2 0.5 4.5 nA Average Input Offset Current Drift2 TCIOS 1.5 40 1.5 85 pA/°C Input Bias Current IB −0.2 +2.4 +4 +2.4 ±6 nA Average Input Bias Current Drift2 TCIB 8 40 15 60 pA/°C Input Voltage Range3 IVR ±13 ±13.5 ±13 ±13.5 V COMMON-MODE REJECTION RATIO CMRR VCM = ±13 V 120 140 110 140 dB POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±18 V 110 120 106 115 dB LARGE-SIGNAL VOLTAGE GAIN4 AVO RL ≥ 2 kΩ, VO = ±10 V 2000 6000 1000 4000 V/mV OUTPUT VOLTAGE SWING VO RL ≥ 2 kΩ ±12 ±13 ±12 ±13 V POWER CONSUMPTION PD VS = ±15 V, no load 60 75 60 75 mW SUPPLY CURRENT ISY VS = ±15 V, no load 20 2.5 2 2.5 mA 1 TCVOS is sample tested. 2 Guaranteed by endpoint limits. 3 Guaranteed by CMRR test condition. 4 To ensure high open-loop gain throughout the ±10 V output range, AVO is tested at −10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and −10 V ≤ VO ≤ +10 V. TEST CIRCUITS 200kΩ 50Ω VOS = VO 4000 VO OP177 – + Figure 3. Typical Offset Voltage Test Circuit OP177 V+ OUTPUT – + – + INPUT V– 20kΩ VOS TRIM RANGE IS TYPICALLY ±3.0mV Figure 4. Optional Offset Nulling Circuit OP177 – + PINOUTS SHOWN FOR P AND Z PACKAGES +20V –20V 20kΩ Figure 5. Burn-In Circuit |
Numéro de pièce similaire - OP177GS |
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Description similaire - OP177GS |
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