AD8325ARUZ-REEL datasheet(3/16 Pages) AD

No de pièce	AD8325ARUZ-REEL

Description	5 V CATV Line Driver Fine Step Output Power Control

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Fabricant	AD [Analog Devices]

Site Internet	http://www.analog.com

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AD8325

LOGIC INPUTS (TTL/CMOS-Compatible Logic) (DATEN, CLK, SDATA, TXEN, SLEEP, V

CC = 5 V: Full Temperature Range)

Parameter

Logic “1” Voltage

Logic “0” Voltage

Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN

Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN

Logic “1” Current (VINH = 5 V) TXEN

Logic “0” Current (VINL = 0 V) TXEN

Logic “1” Current (VINH = 5 V) SLEEP

Logic “0” Current (VINL = 0 V) SLEEP

Min

Typ

Max

Unit

2.1

5.0

V

0

0.8

V

0

20

nA

–600

–100

nA

50

190

mA

–250

–30

mA

50

190

mA

–250

–30

mA

TIMING REQUIREMENTS (Full Temperature Range, V

CC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.)

Parameter

Min

Typ

Max

Unit

Clock Pulsewidth (TWH)

16.0

ns

Clock Period (TC)

32.0

ns

Setup Time SDATA vs. Clock (TDS)

5.0

ns

Setup Time

DATEN vs. Clock (T

ES)

15.0

ns

Hold Time SDATA vs. Clock (TDH)

5.0

ns

Hold Time

DATEN vs. Clock (T

EH)

3.0

ns

Input Rise and Fall Times, SDATA,

DATEN, Clock (T

R, TF)

10

ns

TDS

SDATA

CLK

DATEN

TXEN

ANALOG

OUTPUT

TES

VALID DATA WORD G1

MSB. . . .LSB

GAIN TRANSFER (G1)

TEH

8 CLOCK

CYCLES

GAIN TRANSFER (G2)

TOFF

TGS

SIGNAL AMPLITUDE (p-p)

TON

TC

TWH

VALID DATA WORD G2

Figure 2. Serial Interface Timing

SDATA

CLK

VALID DATA BIT

MSB

MSB-1

MSB-2

TDS

TDH

Figure 3. SDATA Timing

REV. A

–3–

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