Moteur de recherche de fiches techniques de composants électroniques |
|
AD8200 Fiches technique(PDF) 5 Page - Analog Devices |
|
AD8200 Fiches technique(HTML) 5 Page - Analog Devices |
5 / 12 page REV. B AD8200 –5– THEORY OF OPERATION The AD8200 consists of a preamp and buffer arranged as shown in Figure 3. Like-named resistors have equal values. The preamp incorporates a dynamic bridge (subtractor) circuit. Identical networks (within the shaded areas), consisting of RA, RB, RC, and RG, attenuate input signals applied to Pins 1 and 8. Note that when equal amplitude signals are asserted at inputs 1 and 8, and the output of A1 is equal to the common potential (i.e., zero), the two attenuators form a balanced-bridge network. When the bridge is balanced, the differential input voltage at A1, and thus its output, will be zero. Any common-mode voltage applied to both inputs will keep the bridge balanced and the A1 output at zero. Because the resistor networks are carefully matched, the common-mode signal rejec- tion approaches this ideal state. However, if the signals applied to the inputs differ, the result is a difference at the input to A1. A1 responds by adjusting its output to drive RB, by way of RG, to adjust the voltage at its inverting input until it matches the voltage at its noninverting input. By attenuating voltages at Pins 1 and 8, the amplifier inputs are held within the power supply range, even if Pin 1 and Pin 8 input levels exceed the supply, or fall below common (ground.) The input network also attenuates normal (differential) mode voltages. RC and RG form an attenuator that scales A1 feedback, forcing large output signals to balance relatively small differen- tial inputs. The resistor ratios establish the preamp gain at 10. Because the differential input signal is attenuated, and then amplified to yield an overall gain of 10, the amplifier A1 oper- ates at a higher noise gain, multiplying deficiencies such as input offset voltage and noise with respect to Pins 1 and 8. A1 A3 RCM RCM (TRIMMED) 100k RA –IN RG RC RB RA RC RB RG +IN COM A2 RF RF AD8200 Figure 3. Simplified Schematic To minimize these errors while extending the common-mode range, a dedicated feedback loop is employed to reduce the range of common-mode voltage applied to A1, for a given over- all range at the inputs. By offsetting the range of voltage applied to the compensator, the input common-mode range is also offset to include voltages more negative than the power supply. Ampli- fier A3 detects the common-mode signal applied to A1 and adjusts the voltage on the matched RCM resistors to reduce the common-mode voltage range at the A1 inputs. By adjusting the common voltage of these resistors, the common-mode input range is extended while, at the same time, the normal mode signal attenuation is reduced, leading to better performance referred to input. The output of the dynamic bridge taken from A1 is connected to Pin 3 by way of a 100 k Ω series resistor, provided for low- pass filtering and gain adjustment. The resistors in the input networks of the preamp and the buffer feedback resistors are ratio-trimmed for high accuracy. The output of the preamp drives a gain-of-two buffer-amplifier A2, implemented with carefully matched feedback resistors RF. The two-stage system architecture of the AD8200 enables the user to incorporate a low-pass filter prior to the output buffer. By separating the gain into two stages, a full-scale rail-to-rail signal from the preamp can be filtered at Pin 3, and a half-scale signal resulting from filtering can be restored to full scale by the output buffer amp. The source resistance seen by the inverting input of A2 is approximately 100 k Ω, to minimize the effects of A2’s input bias current. However, this current is quite small and errors resulting from applications that mismatch the resistance are correspondingly small. APPLICATIONS The AD8200 difference amplifier is intended for applications where it is required to extract a small differential signal in the presence of large common-mode voltages. The input resistance is nominally 200 k Ω, and the device can tolerate common-mode voltages higher than the supply voltage and lower than ground. The open collector output stage will source current to within 20 mV of ground. 2 1 TEK RUN: 2.5MS/s HI RES VOUT, RL = 10k T VIN CH1 500mV 50mV M 20 s CH1 1.5V CH2 TPC 7. Pulse Response 3 1 TEK RUN: 2.5MS/s AVERAGE VIN CH3 100mV VOUT, RL = 10k MAGNIFIED VOUT 2 CH1 1V CH 2 10mV M 20 s CH1 1.36V TPC 8. Settling Time |
Numéro de pièce similaire - AD8200 |
|
Description similaire - AD8200 |
|
|
Lien URL |
Politique de confidentialité |
ALLDATASHEET.FR |
ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |