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74ACT161 Datasheet(Fiches technique) 1 Page - Fairchild Semiconductor

Numéro de pièce 74ACT161
Description  Synchronous Presettable Binary Counter
Télécharger  11 Pages
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
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© 2003 Fairchild Semiconductor Corporation
DS009931
www.fairchildsemi.com
November 1988
Revised September 2003
74AC161 • 74ACT161
Synchronous Presettable Binary Counter
General Description
The AC/ACT161 are high-speed synchronous modulo-16
binary counters. They are synchronously presettable for
application in programmable dividers and have two types
of Count Enable inputs plus a Terminal Count output for
versatility in forming synchronous multistage counters. The
AC/ACT161 has an asynchronous Master Reset input that
overrides all other inputs and forces the outputs LOW.
Features
s ICC reduced by 50%
s Synchronous counting and loading
s High-speed synchronous expansion
s Typical count rate of 125 MHz
s Outputs source/sink 24 mA
s ACT161 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT
 is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74AC161SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC161SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC161MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC161PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT161SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACT161SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT161MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT161PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names
Description
CEP
Count Enable Parallel Input
CET
Count Enable Trickle Input
CP
Clock Pulse Input
MR
Asynchronous Master Reset Input
P0–P3
Parallel Data Inputs
PE
Parallel Enable Inputs
Q0–Q3
Flip-Flop Outputs
TC
Terminal Count Output




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