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SN54LVTH162373 Fiches technique(PDF) 3 Page - Texas Instruments

No de pièce SN54LVTH162373
Description  3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Download  14 Pages
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI - Texas Instruments

SN54LVTH162373 Fiches technique(HTML) 3 Page - Texas Instruments

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1OE
1LE
1D1
ToSevenOtherChannels
1Q1
2OE
2LE
2D1
2Q1
ToSevenOtherChannels
1
48
47
24
25
36
C1
1D
13
2
C1
1D
PinnumbersshownarefortheDGG,DL,andWDpackages.
Absolute Maximum Ratings
(1)
Recommended Operating Conditions
(1)
SN54LVTH162373
,, SN74LVTH162373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS261M – JULY 1993 – REVISED DECEMBER 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
over recommended operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range(2)
–0.5
7
V
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
–0.5
7
V
VO
Voltage range applied to any output in the high state(2)
–0.5
VCC + 0.5
V
IO
Current into any output in the low state
30
mA
IO
Current into any output in the high state(3)
30
mA
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
DGG package
70
θ
JA
Package thermal impedance(4)
DL package
63
°C/W
GQL/ZQL package
42
Tstg
Storage temperature range
–65
150
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3)
This current flows only when the output is in the high state and VO > VCC.
(4)
The package thermal impedance is calculated in accordance with JESD 51-7.
SN54LVTH162373
SN74LVTH162373
UNIT
MIN
MAX
MIN
MAX
VCC
Supply voltage range
2.7
3.6
2.7
3.6
V
VIH
High-level input voltage
2
2
V
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
5.5
5.5
V
IOH
High-level output current
–12
–12
mA
IOL
Low-level output current
12
12
mA
∆t/∆v
Input transition rise or fall rate
Outputs enabled
10
10
ns/V
∆t/∆V
CC
Power-up ramp rate
200
200
µs/V
TA
Operating free-air temperature
–55
125
–40
85
°C
(1)
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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