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MC100LVEL14DWG Fiches technique(PDF) 2 Page - ON Semiconductor |
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MC100LVEL14DWG Fiches technique(HTML) 2 Page - ON Semiconductor |
2 / 6 page MC100LVEL14 http://onsemi.com 2 6 Q1 Q2 Q3 Q4 17 18 16 15 14 13 12 4 357 8 9 VCC 11 10 Q4 Q3 Q2 Q1 NC SCLK CLK CLK VBB SEL VEE D Q 1 0 Q0 19 20 2 1 VCC Q0 EN Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Pinout (Top View) and Logic Diagram Table 1. PIN DESCRIPTION PIN FUNCTION CLK, CLK ECL Diff Clock Inputs SCLK ECL Scan Clock Input EN ECL Sync Enable SEL ECL Clock Select Input Q0−4, Q0−4 ECL Diff Clock Outputs VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply NC No Connect Table 2. FUNCTION TABLE CLK SCLK SEL EN Q L H X X X X X L H X L L H H X L L L L H L H L H L* *On next negative transition of CLK or SCLK X = Don’t Care Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V VI v VCC VI w VEE 6 to 0 −6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−20 SOIC−20 90 60 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−20 30 to 35 °C/W Tsol Wave Solder Pb Pb−Free <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. |
Numéro de pièce similaire - MC100LVEL14DWG |
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