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SN65LVDS049 Fiches technique(PDF) 1 Page - Texas Instruments

No de pièce SN65LVDS049
Description  DUAL LVDS DIFFERENTIAL DRIVERS AND RECEIVERS
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Fabricant  TI [Texas Instruments]
Site Internet  http://www.ti.com
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SN65LVDS049 Fiches technique(HTML) 1 Page - Texas Instruments

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D2
R1
R2
D1
AND
ROUT1
ROUT2
DIN2
DIN1
EN
EN
DOUT1+
DOUT1−
DOUT2−
DOUT2+
RIN2−
RIN2+
RIN1−
RIN1+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RIN1-
RIN1+
RIN2+
RIN2-
DOUT2-
DOUT2+
DOUT1+
DOUT1-
EN
ROUT1
ROUT2
GND
VCC
DIN2
DIN1
EN
SN65LVDS049
SLLS575 – AUGUST 2003
DUAL LVDS DIFFERENTIAL DRIVERS AND RECEIVERS
The intended application of this device and signaling
FEATURES
technique is for point-to-point baseband data trans-
DS90LV049 Compatible
mission over controlled impedance media of approxi-
Up to 400 Mbps Signaling Rates
mately 100-
Ω characteristic impedance. The trans-
mission media may be printed-circuit board traces,
Flow-Through Pin-out
backplanes, or cables. (Note: The ultimate rate and
50 ps Driver Channel-to-Channel Skew (Typ)
distance of data transfer is dependent upon the attenu-
50 ps Receiver Channel-to-Channel Skew
ation characteristics of the media, the noise coupling to
the environment, and other application specific charac-
(Typ)
teristics)
3.3-V Power Supply
The SN65LVDS049 is characterized for operation from
High-Impedance Disable for all Outputs
–40
°C to 85°C
Internal Failsafe Biasing of Receiver Inputs
1.4 ns Driver Propagation Delay (Typ)
1.9 ns Receiver Propagation Delay (Typ)
FUNCTIONAL DIAGRAM
High Impedance Bus Pins on Power Down
ANSI TIA/EIA-644-A Compliant
Receiver Input and Driver Output ESD Ex-
ceeds 10 kV
16-pin TSSOP Package
APPLICATIONS
Full-duplex LVDS Communications of Clock
and Data
Printers
DESCRIPTION
The SN65LVDS049 is a dual flow-through differential
line driver-receiver pair that uses low-voltage differen-
tial signaling (LVDS) to achieve signaling rates as high
as 400 Mbps. The TIA/EIA-644-A standard compliant
electrical interface provides a minimum differential out-
PW PACKAGE (Marked as LVDS049)
(TOP VIEW)
put voltage magnitude of 250 mV into a 100-
Ω load and
receipt of signals with up to 1 V of ground potential
difference between a transmitter and receiver. The
LVDS receivers have internal failsafe biasing that
places the outputs into a known high state for uncon-
nected differential inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily in-
clude testing of all parameters.


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