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MC74HC595A Fiches technique(PDF) 4 Page - ON Semiconductor

No de pièce MC74HC595A
Description  8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs High−Performance Silicon−Gate CMOS
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74HC595A Fiches technique(HTML) 4 Page - ON Semiconductor

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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Unit
Guaranteed Limit
VCC
V
Test Conditions
Parameter
Symbol
Unit
v 125_C
v 85_C
– 55 to 25
_C
VCC
V
Test Conditions
Parameter
Symbol
VOL
Maximum Low−Level Output
Voltage, QA − QH
Vin = VIH or VIL
|Iout| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL
|Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH
Minimum High−Level Output
Voltage, SQH
Vin = VIH or VIL
IIoutI v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL
|Iout| v 2.4 mA
IIoutI v 4.0 mA
IIoutIv 5.2 mA
3.0
4.5
6.0
2.98
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
VOL
Maximum Low−Level Output
Voltage, SQH
Vin = VIH or VIL
IIoutI v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL
|Iout| v 2.4 mA
IIoutI v 4.0 mA
IIoutIv 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Iin
Maximum Input Leakage
Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
mA
IOZ
Maximum Three−State
Leakage
Current, QA − QH
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
± 0.5
± 5.0
± 10
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
lout = 0 mA
6.0
4.0
40
160
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
VCC
V
– 55 to 25
_C
v 85_C
v 125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Shift Clock to SQH
(Figures 1 and 7)
2.0
3.0
4.5
6.0
140
100
28
24
175
125
35
30
210
150
42
36
ns
tPHL
Maximum Propagation Delay, Reset to SQH
(Figures 2 and 7)
2.0
3.0
4.5
6.0
145
100
29
25
180
125
36
31
220
150
44
38
ns
tPLH,
tPHL
Maximum Propagation Delay, Latch Clock to QA − QH
(Figures 3 and 7)
2.0
3.0
4.5
6.0
140
100
28
24
175
125
35
30
210
150
42
36
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to QA − QH
(Figures 4 and 8)
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to QA − QH
(Figures 4 and 8)
2.0
3.0
4.5
6.0
135
90
27
23
170
110
34
29
205
130
41
35
ns


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