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MC74HC573A Fiches technique(PDF) 4 Page - ON Semiconductor

No de pièce MC74HC573A
Description  Octal 3−State Noninverting Transparent Latch High−Performance Silicon−Gate CMOS
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74HC573A Fiches technique(HTML) 4 Page - ON Semiconductor

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MC74HC573A
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to 25
_C
v 85_C
v 125_C
tPLH,
tPHL
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
2.0
3.0
4.5
6.0
150
100
30
26
190
140
38
33
225
180
45
38
ns
tPLH,
tPHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
2.0
3.0
4.5
6.0
160
105
32
27
200
145
40
34
240
190
48
41
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
2.0
3.0
4.5
6.0
60
27
12
10
75
32
15
13
90
36
18
15
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum 3−State Output Capacitance (Output in High−Impedance State)
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Enabled Output)*
Typical @ 25
°C, VCC = 5.0 V
pF
23
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
Figure
VCC
V
Guaranteed Limit
Unit
– 55 to 25
_C
v 85_C
v 125_C
Min
Max
Min
Max
Min
Max
tsu
Minimum Setup Time, Input D to Latch Enable
4
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
th
Minimum Hold Time, Latch Enable to Input D
4
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Latch Enable
2
2.0
3.0
4.5
6.0
75
60
15
13
95
80
19
16
110
90
22
19
ns
tr, tf
Maximum Input Rise and Fall Times
1
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns


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Numéro de composants électroniques

No de pièceDescriptionHtml ViewFabricant
MC74HC373A_05 Octal 3−State Non−Inverting Transparent Latch High−Performance Silicon−Gate CMOS 1  2  3  4  5  More ON Semiconductor
MC74HC244A_06 Octal 3−State Noninverting Buffer/Line Driver/ Line Receiver High−Performance Silicon−Gate CMOS 1  2  3  4  5  More ON Semiconductor
MC74HC245A_06 Octal 3−State Noninverting Bus Transceiver High−Performance Silicon−Gate CMOS 1  2  3  4  5  More ON Semiconductor
MC74HC541A_05 Octal 3−State Noninverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS 1  2  3  4  5  More ON Semiconductor
MC74HCT373A_06 Octal 3−State Noninverting Transparent Latch with LSTTL−Compatible Inputs 1  2  3  4  5  More ON Semiconductor
MC74HC374A_05 Octal 3−State Non−Inverting D Flip−Flop High−Performance Silicon−Gate CMOS 1  2  3  4  5  More ON Semiconductor
MC74HC540A_05 Octal 3−State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS 1  2  3  4  5  More ON Semiconductor
MC74HC273A_05 Octal D Flip−Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS 1  2  3  4  5  More ON Semiconductor
IDT74LVC573A 3.3V CMOS OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O 1  2  3  4  5  More Integrated Device Technology
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