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MC74HC161A Fiches technique(PDF) 5 Page - ON Semiconductor

No de pièce MC74HC161A
Description  Presettable Counters High−Performance Silicon−Gate CMOS
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC74HC161A Fiches technique(HTML) 5 Page - ON Semiconductor

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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
Figure
VCC
V
Guaranteed Limit
Unit
– 55 to 25_C
v 85_C
v 125_C
fmax
Maximum Clock Frequency
(50% Duty Cycle)
(Note 8)
4, 10
2.0
3.0
4.5
6.0
6
15
30
35
5
12
24
28
4
10
20
24
MHz
tPLH
Maximum Propagation Delay,
Clock to Q
4, 10
2.0
3.0
4.5
6.0
120
75
20
16
160
120
23
20
200
150
28
22
ns
tPHL
4, 10
2.0
3.0
4.5
6.0
145
100
22
18
185
135
25
20
220
150
30
23
ns
tPHL
Maximum Propagation Delay,
Reset to Q (HC161A Only)
5, 10
2.0
3.0
4.5
6.0
145
100
20
17
185
135
22
19
220
150
25
21
ns
tPLH
Maximum Propagation Delay,
Enable T to Ripple Carry Out
6, 10
2.0
3.0
4.5
6.0
110
60
16
14
150
115
18
15
190
140
20
17
ns
tPHL
6, 10
2.0
3.0
4.5
6.0
135
100
18
15
175
130
20
16
210
160
22
20
ns
tPLH
Maximum Propagation Delay,
Clock to Ripple Carry Out
4, 10
2.0
3.0
4.5
6.0
120
75
22
18
160
135
27
22
200
150
30
25
ns
tPHL
4, 10
2.0
3.0
4.5
6.0
145
100
22
20
185
135
28
24
220
150
35
28
ns
tPHL
Maximum Propagation Delay,
Reset to Ripple Carry Out
(HC161A Only)
5, 10
2.0
3.0
4.5
6.0
155
120
22
18
190
140
26
22
230
155
30
25
ns
tTLH,
tTHL
Maximum Output Transition Time,
Any Output
5, 10
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
Cin
Maximum Input Capacitance
4, 10
10
10
10
pF
8. Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out
propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However,
if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable.
See Applications information in this data sheet.
9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Gate) (Note 10)
Typical @ 25°C, VCC = 5.0 V
pF
45
10.Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).


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