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MC10H209 Fiches technique(PDF) 1 Page - ON Semiconductor |
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MC10H209 Fiches technique(HTML) 1 Page - ON Semiconductor |
1 / 6 page © Semiconductor Components Industries, LLC, 2006 February, 2006 − Rev. 7 1 Publication Order Number: MC10H209/D MC10H209 Dual 4−5−Input OR/NOR Gate Description The MC10H209 is a Dual 4−5−input OR/NOR gate. This MECL part is a functional/pinout duplication of the MECL III part MC1688. Features • Propagation Delay Average, 0.75 ns Typical • Power Dissipation 125 mW Typical • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K™ Compatible • Pb−Free Packages are Available* LOGIC DIAGRAM DIP PIN ASSIGNMENT VCC1 AOUT AOUT AIN AIN AIN AIN VEE VCC2 BOUT BOUT BIN BIN BIN BIN BIN 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 12 15 13 11 10 9 7 6 5 4 14 2 3 Pin assignment is for Dual−in−Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. CDIP−16 L SUFFIX CASE 620A MARKING DIAGRAMS* PDIP−16 P SUFFIX CASE 648 http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. ORDERING INFORMATION SOEIAJ−16 CASE 966 16 1 16 1 MC10H209P AWLYYWW 1 16 MC10H209L AWLYYWW A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G= Pb−Free Package 10H209 ALYWG PLLC−20 FN SUFFIX CASE 775 20 1 10H209G AWLYYWW 120 |
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