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74F534 Fiches technique(PDF) 2 Page - Fairchild Semiconductor

No de pièce 74F534
Description  Octal D-Type Flip-Flop with 3-STATE Outputs
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Fabricant  FAIRCHILD [Fairchild Semiconductor]
Site Internet  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74F534 Fiches technique(HTML) 2 Page - Fairchild Semiconductor

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Unit Loading/Fan Out
Function Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
Z
= High Impedance
 = LOW-to-HIGH Clock Transition
O0 = Value stored from previous clock cycle
Functional Description
The 74F534 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE complementary out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold times requirements on the LOW-to-HIGH clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
D0–D7
Data Inputs
1.0/1.0
20
µA/−0.6 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
µA/−0.6 mA
OE
3-STATE Output Enable Input (Active LOW)
1.0/1.0
20
µA/−0.6 mA
O0–O7
Complementary 3-STATE Outputs
150/40(33.3)
−3 mA/24 mA (20 mA)
Inputs
Output
CP
OE
DO

LH
L

LL
H
LL
X
O0
XH
X
Z


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