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MC100E195FNR2 Fiches technique(PDF) 2 Page - ON Semiconductor

No de pièce MC100E195FNR2
Description  5V ECL Programmable Delay Chip
Download  11 Pages
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Fabricant  ONSEMI [ON Semiconductor]
Site Internet  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

MC100E195FNR2 Fiches technique(HTML) 2 Page - ON Semiconductor

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MC10E195, MC100E195
http://onsemi.com
2
D2
D3
D4
D5
D6
D7
NC
NC
NC
EN
NC
NC
VCC
VCCO
Q
Q
VCCO
D1
D0
LEN
VEE
IN
IN
VBB
25
24
23
22
21
20
19
26
27
28
1
2
3
4
18
17
16
15
14
13
12
56
7
8
9
10
11
Figure 1. Pinout: 28-Lead PLCC
(Top View)
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
*All VCC and VCCO pins are tied together on the die.
MC10E195
MC100E195
Table 1. PIN DESCRIPTION
PIN
FUNCTION
IN/IN
EN
D[0:7]
Q/Q
LEN
SET MIN
SET MAX
CASCADE, CASCADE
VBB
VCC, VCCO
VEE
NC
ECL Signal Input
ECL Input Enable
ECL MUX Select Inputs
ECL Signal Output
ECL Latch Enable
ECL Min Delay Set
ECL Max Delay Set
ECL Cascade Signal
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
Table 2. TRUTH TABLE
EN.
L
Q = IN
EN
H
Q Logic Low
LEN
L
Pass Through D[0:10]
LEN
H
Latch D[0:10]
SETMIN
L
Normal Mode
SETMIN
H
Min Delay Path
SETMAX
L
Normal Mode
SETMAX
H
Max Delay Path
1
Figure 2. Logic Diagram − Simplified
VBB
IN
IN
EN
LEN
SET MIN
SET MAX
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
11
1
1
0
1
Q
Q
CASCADE
CASCADE
CASCADE
7 BIT LATCH
LEN
Q
LATCH
D
4 GATES
8 GATES
16 GATES
* 1.25
* 1.5
D0
D1
D2
D3
D4
D5
D6
D7
* delays are 25% or 50% longer than
* standard (standard ≈ 80 ps)
VEE


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