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MC100E175FN Fiches technique(PDF) 1 Page - ON Semiconductor |
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MC100E175FN Fiches technique(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2006 December, 2006 − Rev. 9 1 Publication Order Number: MC10E175/D MC10E175, MC100E175 5VECL 9-Bit Latch With Parity Description The MC10E/100E175 is a 9-bit latch. It also features a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type select (L = even parity, H = odd parity), and using ODDPAR as the byte parity output. The LEN pin latches the data when asserted with a logical high and makes the latch transparent when placed at a logic low level. Features • 9-Bit Latch • Parity Detection/Generation • 800 ps Max. D to Output • Reset • PECL Mode Operating Range: VCC = 4.2 V to 5.5 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.5 V • Internal Input 50 kW Pulldown Resistors • ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V Charged Device MOdel; > 2 kV • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity Level: Pb = 1 Pb−Free = 3 For Additional Information, see Application Note AND8003/D • Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 • Transistor Count = 416 devices • Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MARKING DIAGRAM* xxx = 10 or 100 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package PLCC−28 FN SUFFIX CASE 776 MCxxxE175FNG AWLYYWW 1 http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ORDERING INFORMATION |
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