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74VCX16374 Fiches technique(PDF) 1 Page - ON Semiconductor |
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74VCX16374 Fiches technique(HTML) 1 Page - ON Semiconductor |
1 / 11 page © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 6 1 Publication Order Number: 74VCX16374/D 74VCX16374 Low−Voltage 1.8/2.5/3.3V 16−Bit D−Type Flip−Flop With 3.6 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74VCX16374 is an advanced performance, non−inverting 16−bit D−type flip−flop. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The VCX16374 is byte controlled, with each byte functioning identically, but independently. Each byte has separate Output Enable and Clock Pulse inputs. These control pins can be tied together for a full 16−bit operation. When operating at 2.5 V (or 1.8 V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6 V. The 74VCX16374 consists of 16 edge−triggered flip−flops with individual D−type inputs and 3.6 V−tolerant 3−state outputs. The clocks (CPn) and Output Enables (OEn) are common to all flip−flops within the respective byte. The flip−flops will store the state of individual D inputs that meet the setup and hold time requirements on the LOW−to−HIGH Clock (CP) transition. With the OE LOW, the contents of the flip−flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. The OE input level does not affect the operation of the flip−flops. Features • Designed for Low Voltage Operation: VCC = 1.65 V − 3.6 V • 3.6 V Tolerant Inputs and Outputs • High Speed Operation: 3.0 ns max for 3.0 V to 3.6 V 3.9 ns max for 2.3 V to 2.7 V 7.8 ns max for 1.65 V to 1.95 V • Static Drive: ±24 mA Drive at 3.0 V ±18 mA Drive at 2.3 V ±6 mA Drive at 1.65 V • Supports Live Insertion and Withdrawal • IOFF Specification Guarantees High Impedance When VCC = 0 V • Near Zero Static Supply Current in All Three Logic States (20 mA) Substantially Reduces System Power Requirements • Latchup Performance Exceeds ±250 mA @ 125°C • ESD Performance: Human Body Model >2000 V Machine Model >200 V • All Devices in Package TSSOP are Inherently Pb−Free* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MARKING DIAGRAM A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week TSSOP−48 DT SUFFIX CASE 1201 1 48 VCX16374 AWLYYWW 1 48 PIN NAMES Function Output Enable Inputs Clock Pulse Inputs Inputs Outputs Pins OEn CPn D0−D15 O0−O15 Device Package Shipping† ORDERING INFORMATION 74VCX16374DT TSSOP (Pb−Free) 39 / Rail 74VCX16374DTR TSSOP (Pb−Free) 2500 / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. http://onsemi.com |
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