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2

Unit Loading/Fan Out

Functional Description

The 74F374 consists of eight edge-triggered flip-flops with

individual D-type inputs and 3-STATE true outputs. The

buffered clock and buffered Output Enable are common to

all flip-flops. The eight flip-flops will store the state of their

individual D inputs that meet the setup and hold time

requirements on the LOW-to-HIGH Clock (CP) transition.

With the Output Enable (OE) LOW, the contents of the

eight flip-flops are available at the outputs. When the OE is

HIGH, the outputs go to the high impedance state. Opera-

tion of the OE input does not affected the state of the flip-

flops.

Truth Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

Z

= High Impedance

 = LOW-to-HIGH Clock Transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names

Description

U.L.

HIGH/LOW

Data Inputs

1.0/1.0

20

µA/−0.6 mA

CP

Clock Pulse Input (Active Rising Edge)

1.0/1.0

20

µA/−0.6 mA

OE

3-STATE Output Enable Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

3-STATE Outputs

150/40 (33.3)

−3 mA/24 mA (20 mA)

Inputs

Internal

Output

CP

OE

Register

H



LH

H

L



LL

L

XX

H

X

Z