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SN74ABT18502PMR Fiches technique(PDF) 4 Page - Texas Instruments |
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SN74ABT18502PMR Fiches technique(HTML) 4 Page - Texas Instruments |
4 / 30 page SN74ABT18502 SCAN TEST DEVICE WITH 18-BIT REGISTERED BUS TRANSCEIVER SCBS753 – FEBRUARY 2002 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions PIN NAME DESCRIPTION GND Ground TCK Test clock. One of four pins required by IEEE Std 1149.1-1990. Test operations of the device are synchronous to the test clock. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. TDI Test data input. One of four pins required by IEEE Std 1149.1-1990. TDI is the serial input for shifting data through the instruction register (IR) or selected data register (DR). An internal pullup forces TDI to a high level if left unconnected. TDO Test data output. One of four pins required by IEEE Std 1149.1-1990. TDO is the serial output for shifting data through the IR or selected DR. TMS Test mode select. One of four pins required by IEEE Std 1149.1-1990. The TMS input directs the device through its TAP controller states. An internal pullup forces TMS to a high level if left unconnected. VCC Supply voltage 1A1–1A9, 2A1– 2A9 Normal-function A-bus I/O ports (see function table for normal-mode logic) 1B1–1B9, 2B1– 2B9 Normal-function B-bus I/O ports (see function table for normal-mode logic) 1CLKAB, 1CLKBA, 2CLKAB, 2CLKBA Normal-function clock inputs (see function table for normal-mode logic) 1LEAB, 1LEBA, 2LEAB, 2LEBA Normal-function latch enables (see function table for normal-mode logic) 1OEAB, 1OEBA, 2OEAB, 2OEBA Normal-function output enables (see function table for normal-mode logic) |
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