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CDC318 Fiches technique(PDF) 5 Page - Texas Instruments |
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CDC318 Fiches technique(HTML) 5 Page - Texas Instruments |
5 / 13 page CDC318 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS587B – JANUARY 1997 – REVISED MARCH 1998 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC –0.5 V to 4.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, VI (see Note 1) –0.5 V to 4.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, VI (SCLOCK, SDATA) (see Note 1) –0.5 V to 6.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output voltage range, VO (SDATA) (see Note 1) –0.5 V to 6.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage range applied to any output in the high or power-off state, VO –0.5 V to VCC +0.5 V . . . . . . . . . . . . . Current into any output in the low state (except SDATA), IO 48 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current into SDATA in the low state, IO 12 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current, IIK (VI < 0) (SCLOCK) –50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp current, IOK (VO < 0) (SDATA) –50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package thermal impedance, θJA (see Notes 2 and 3) 84 °C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –65 °C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 _C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. The absolute maximum power dissipation allowed at TA = 55°C (in still air) is 1.2 W. 3. Thermal impedance ( ΘJA) can be considerably lower if the device is soldered on the PCB board with a copper layer underneath the package. A simulation on a PCB board (3 in. × 3 in.) with two internal copper planes (1 oz. cu, 0.036 mm thick) and 0.071 mm cu (202) in area underneath the package, resulted in ΘJA = 60°C/W. This would allow 1.2 W total power dissipation at TA = 70°C. recommended operating conditions (see Note 4) MIN TYP MAX UNIT VCC 3.3-V core supply voltage 3.135 3.465 V A, OE 2 VCC+0.3 V VIH High-level input voltage SDATA, SCLOCK (see Note 3) 2.2 5.5 V A, OE –0.3 0.8 V VIL Low-level input voltage SDATA, SCLOCK (see Note 3) 0 1.04 V IOH High-level output current Y outputs 1 mA IOL Low-level output current Y outputs –1 mA ri Input resistance to VCC SDATA, SCLOCK (see Note 3) 140 k Ω f(SCL) SCLOCK frequency 100 kHz t(BUS) Bus free time 4.7 µs tsu(START) START setup time 4.7 µs th(START) START hold time 4 µs tw(SCLL) SCLOCK low pulse duration 4.7 µs tw(SCLH) SCLOCK high pulse duration 4 µs tr(SDATA) SDATA input rise time 1000 ns tf(SDATA) SDATA input fall time 300 ns tsu(SDATA) SDATA setup time 250 ns th(SDATA) SDATA hold time 0 ns tsu(STOP) STOP setup time 4 µs TA Operating free-air temperature 0 70 °C NOTE 4: The CMOS-level inputs fall within these limits: VIH min = 0.7 × VCC and VIL max = 0.3 × VCC. |
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Description similaire - CDC318 |
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