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C5001
Low Skew Multiple Frequency PCI Clock Generator with EMI Reducing SSCG.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev. 2.1
6/14/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
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Product Features
S
Produces PCI output clocks that are individually
selectable for 33.3 or 66.6 MHz under I
2C or
strapping control.
S
Separate output buffer power supply for reduced
noise, crosstalk and jitter.
S
input clock frequency standard 14.31818 MHz
S
Output clocks frequency individually selectable via
I
2C or hardware bi-directional pin strapping.
S
SSCG EMI reduction at 1.0% width
S
Individual clock disables via I
2C control
S
All output clocks skewed within a 500 pS window
S
Cycle to Cycle jitter
± 250 pS
S
Output duty cycle is automatically 50% (
±10%)
adjusted
S
Clock feed through mode and OE pins for logic
testing
S
Glitchless clock enabling and disabling transitions
S
28-pin TSSOP or SSOP package
Block Diagram
Output Enable logic Functionality Table
OE
CLK(0:9)
PLL
1 (HIGH)
Enabled
Running
0 (LOW)
Tri State
Running
Pin Configuration
VDD1
REF-CLK0/S0
CLK1/S1
VSS
VDD2
CLK2/S2
CLK3/S3
VSS
VDD3
CLK4/S4
CLK5/S5
VSS
VDD4
CLK6/S6
VDD
XIN
XOUT
VSS
OE
SCLK
SDATA
VSS
VSS
CLK9/S9
CLK8/S8
VDD5
VSS
CLK7/S7
28
27
26
25
24
23
22
21
20
19
18
17
16.
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
XIN
SCLK
SDATA
XOUT
CLK4/S4
CLK1/S1
REF-
CLK0/S0
CLK2/S2
CLK3/S3
CLK7/S7
CLK8/S8
CLK9/S9
CLK5/S5
CLK6/S6
I2C
LOGIC
÷1 ÷2
÷1 ÷2
÷1 ÷2
÷1 ÷2
÷1 ÷2
÷1 ÷2
÷1 ÷2
÷1 ÷2
÷1 ÷2
÷1 ÷2
÷4, ÷8
PLL
OE
M
U
X
Reference
Oscillator