Moteur de recherche de fiches techniques de composants électroniques |
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IP2003A Fiches technique(PDF) 1 Page - International Rectifier |
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IP2003A Fiches technique(HTML) 1 Page - International Rectifier |
1 / 10 page www.irf.com 1 iP2003A Features: Full function multiphase building block Output current 40A continuous with no derating up to T PCB = 100°C and TCASE = 100°C Operating frequency up to 1.0 MHz Proprietary packaging enables ultra low Rthj-case top Efficient dual sided cooling Small footprint low profile (9mm x11mm x 2.2mm) package Optimized for very low power losses LGA interface Ease of design Synchronous Buck Multiphase Optimized LGA Power Block Integrated Power Semiconductors, Drivers & Passives Description The iP2003A is a fully optimized solution for high current synchronous buck multiphase applications. Board space and design time are greatly reduced because most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 9mm x 11mm x 2.2mm power block. The only additional components required for a complete multiphase converter are a PWM controller, the output inductors, and the input and output capacitors. iPOWIR technology offers designers an innovative board space saving solution for applications requiring high power densities. iPOWIR technology eases design for applications where component integration offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat transfer and component selection. iP2003A Power Block 10/19/05 iP2003A Internal Block Diagram ENABLE PWM MOSFET Driver with dead time control V IN V SW PGND PRDY V DD V SWS2 V SWS1 MOSFET Driver with dead time control V IN V SW PGND PRDY V DD V SWS2 V SWS1 Pin # Pin Name Pin Function 1 VDD Supply voltage for the internal circuitry. 2 ENABLE W hen set to logic level high, internal circuitry of the device is enabled. W hen set to logic level low, the PRDY pin is forced low, the Control and Sychronous switches are turned off, and the supply current reduces to 10µ A. 3 PW M TTL-level input signal to M OSFET drivers. 4 PRDY Power Ready - This pin indicates the status of ENAB LE or VDD. This output will be driven low when ENABLE is logic low or when VDD is less than 4.4V (typ.). W hen ENAB LE is logic high and VDD is greater than 4.4V (typ.), this output is driven high. This output has a 10mA source and 1mA sink capability. 5, 7 PGND Power Ground - connection to the ground of bulk and filter capacitors. 6 VSW Switching Node - connection to the output inductor. 8 VIN Input voltage pin. External bypass ceramic capacitors must be added directly next to the block. 9 VSWS1 Floating pin. For internal use. Externally, short to VSWS2 pin only. 10 VSWS2 Floating pin. For internal use. Externally, short to VSWS1 pin only. PD-96987A |
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