TPIC5423L

4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL

POWER DMOS ARRAY

SLIS045 – NOVEMBER 1994

2–4

POST OFFICE BOX 655303

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td(on)

Turn-on delay time

34

70

td(off)

Turn-off delay time

VDD = 25 V,

RL = 40 Ω,ten = 10 ns,

20

40

ns

tr

Rise time

DD

tdis = 10 ns,

L

See Figure 2

en

28

55

ns

tf

Fall time

15

30

Qg

Total gate charge

V48 V

I

0 625 A

V5 V

6.6

8

Qgs(th) Threshold gate-to-source charge

VDS = 48 V,

See Figure 3

ID = 0.625 A,

VGS = 5 V,

0.5

0.6

nC

Qgd

Gate-to-drain charge

See Figure 3

2.6

3.2

LD

Internal drain inductance

5

nH

LS

Internal source inductance

5

nH

Rg

Internal gate resistance

0.25

Ω

thermal resistance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R

θJA

Junction-to-ambient thermal resistance

See Notes 4 and 7

90

R

θJB

Junction-to-board thermal resistance

See Notes 5 and 7

49

°C/W

R

θJP

Junction-to-pin thermal resistance

See Notes 6 and 7

28

NOTES:

4. Package mounted on an FR4 printed-circuit board with no heatsink.

5. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board.

6. Package mounted in intimate contact with infinite heatsink.

7. All outputs with equal power.

PARAMETER MEASUREMENT INFORMATION

trr(SD)

IRM†

25% of IRM†

Shaded Area = QRR

VDS = 48 V

VGS = 0

TJ = 25°C

Z1 – Z4‡

Reverse di/dt = 100 A/

µs

† IRM = maximum recovery current

‡ The above waveform is representative of D1, D2, D3, and D4 in shape only.

0

– 0.5

– 1

– 1.5

– 2

– 2.5

– 3

Time – ns

0

50

100

150

200

250

300

1

0.5

350

400

450

500

Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode