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CDCD5704PW Fiches technique(PDF) 2 Page - Texas Instruments |
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CDCD5704PW Fiches technique(HTML) 2 Page - Texas Instruments |
2 / 17 page www.ti.com B0137-01 REFCLK BYPASS CLK0 VSSP VDDP VDDC VDD VSSC VSS VDD VDDC VDDP CLK0B CLK1 CLK1B CLK2 CLK2B CLK3 CLK3B REFCLKB MUX CLK0 SDA SCL ID0 ID1 CLk1 CLK2 CLK3 EN CLK0 CurrentandVoltage Reference ISET RSET PLL 1 300MHzto667MHz Power Down Logic SerialInterface ControlLogic CDCD5704 SCAS823 – DECEMBER 2006 The bypass mode routes the input clock REFCLK to the differential output buffers, bypassing the PLL. To ensure that the CDCD5704 clock generator always performs correctly, the device switches off the PLL and the outputs are in the high-impedance state, once the clock input is below 10 MHz. If the supply voltage VDD is less than VPUC, all logic gates are reset, the PLL is powered down, and the outputs are in the high-impedance state. Therefore, the device only starts its operation if these minimum requirements are met. Because the CDCD5704 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to the start of stabilization time. The device operates from a single 2.5-V supply voltage. The CDCD5704 device is characterized for operation from 0 °C to 70°C. FUNCTIONAL BLOCK DIAGRAM 2 Submit Documentation Feedback |
Numéro de pièce similaire - CDCD5704PW |
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Description similaire - CDCD5704PW |
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