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LC4064B-5T100C Datasheet(Fiches technique) 3 Page - Lattice Semiconductor

Numéro de pièce LC4064B-5T100C
Description  3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
Télécharger  74 Pages
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Fabricant  LATTICE [Lattice Semiconductor]
Site Internet  http://www.latticesemi.com
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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
3
Figure 1. Functional Block Diagram
The I/Os in the ispMACH 4000 are split into two banks. Each bank has a separate I/O power supply. Inputs can
support a variety of standards independent of the chip or bank power supply. Outputs support the standards com-
patible with the power supply provided to the bank. Support for a variety of standards helps designers implement
designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is con-
nected to VCCO of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.
ispMACH 4000 Architecture
There are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has
36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be
connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still
must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and
predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associ-
ated I/O cells in the I/O block.
Generic Logic Block
The ispMACH 4000 GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock
generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou-
pled from macrocells through the ORP. Figure 2 illustrates the GLB.
I/O
Block
ORP
ORP
16
16
36
Generic
Logic
Block
Generic
Logic
Block
I/O
Block
ORP
ORP
16
36
Generic
Logic
Block
Generic
Logic
Block
I/O
Block
I/O
Block
36
36
16
16
16
16
16




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