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ESS Technology, Inc.
SAM0462-031704
5
ES6028 PRODUCT BRIEF
ES6028 PIN DESCRIPTION
DCLK
105
I
Clock input to PLL.
YUV0
106
O
YUV pixel 0 output data.
CAMIN2
I
Camera input 2.
UDAC
O
Video DAC output.
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
YUV1
107
O
YUV pixel 1output data.
VREF
I
Internal voltage reference to video DAC. Bypass to ground with 0.1-
µF capacitor.
YUV2
108
O
YUV pixel 2 output data.
CDAC
O
Video DAC output. Refer to description and matrix for UDAC pin 106.
YUV3
109
O
YUV pixel 3 output data.
COMP
I
Compensation input. Bypass to ADVEE with 0.1-
µF capacitor.
YUV4
110
O
YUV pixel 4 output data.
RSET
I
DAC current adjustment resistor input.
ADVEE
111
P
Analog power for video DAC.
ADVSS
112
G
Analog ground for video DAC.
Table 1
ES6028 Pin Description (Continued)
Name
Pin Numbers
I/O
Definition
Pin
114
113
108
106
Value
DAC V
DAC Y
DAC C
DAC U
0
CVBS1
Y
C
N/A
1
CVBS1
Y
C
CVBS2
2N/A
Y
C
N/A
3
CVBS1
N/A
N/A
CVBS2
4
CVBS1
N/A
N/A
N/A
5
CVBS1
Y
Pb
Pr
6N/A
Y
Pb
Pr
7
SYNC
G
B
R
8
CHROMA
Y
Pb
Pr
9
CVBS1
G
B
R
10
CVBS1
G
R
B
11
SYNC
G
R
B
12
N/A
Y
Pr
Pb
13
CVBS1
Y
Pr
Pb
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