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FWIXPPCD0QE001 Fiches technique(PDF) 6 Page - Intel Corporation |
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FWIXPPCD0QE001 Fiches technique(HTML) 6 Page - Intel Corporation |
6 / 226 page Contents 6 Datasheet Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 5.2.5 The Fiber Interface .............................................................................................. 166 5.2.6 LED Circuit........................................................................................................... 167 5.3 Typical Application Circuits............................................................................................... 168 6.0 Test Specifications.................................................................................................................... 173 7.0 Register Definitions................................................................................................................... 199 8.0 Package Specifications............................................................................................................. 221 9.0 Ordering Information................................................................................................................. 227 Figures 1 Intel® LXT9785/LXT9785E Block Diagram................................................................................. 19 2 Intel® LXT9785 and Intel® LXT9785E RMII 208-Pin PQFP Assignments .................................. 21 3 Intel® LXT9785/LXT9785E SMII 208-Pin PQFP Assignments ................................................... 26 4 Intel® LXT9785/LXT9785E SS-SMII 208-Pin PQFP Assignments ............................................. 31 5 Intel® LXT9785/LXT9785E 241-Ball BGA23 Assignments (Top View)...................................... 51 6 Intel® LXT9785MBC 196-Ball BGA15 Assignments (Top View) ................................................ 98 7 Intel® LXT9785/LXT9785E Interfaces ...................................................................................... 118 8 Intel® LXT9785/LXT9785E Internal Loopback.......................................................................... 120 9 Intel® LXT9785/LXT9785E Management Interface Read Frame Structure.............................. 122 10 Intel® LXT9785/LXT9785E Management Interface Write Frame Structure .............................. 122 11 Intel® LXT9785/LXT9785E Port Address Scheme ................................................................... 123 12 Intel® LXT9785/LXT9785E Interrupt Logic ............................................................................... 124 13 Intel® LXT9785/LXT9785E Initialization Sequence .................................................................. 127 14 Intel® LXT9785/LXT9785E Auto-Negotiation Operation........................................................... 131 15 Intel® LXT9785/LXT9785E Typical SMII Interface Diagram ..................................................... 133 16 Intel® LXT9785/LXT9785E Typical SMII Quad Sectionalization Diagram................................ 134 17 Intel® LXT9785/LXT9785E 100 Mbps Serial MII Data Flow ..................................................... 135 18 Intel® LXT9785/LXT9785E Serial MII Transmit Synchronization ............................................. 136 19 Intel® LXT9785/LXT9785E Serial MII Receive Synchronization .............................................. 137 20 Intel® LXT9785/LXT9785E Typical SS-SMII Interface Diagram ............................................... 139 21 Intel® LXT9785/LXT9785E Typical SS-SMII Quad Sectionalization Diagram .......................... 140 22 Intel® LXT9785/LXT9785E SS-SMII Transmit Timing .............................................................. 141 23 Intel® LXT9785/LXT9785E SS-SMII Receive Timing ............................................................... 141 24 Intel® LXT9785/LXT9785E RMII Data Flow ............................................................................. 142 25 Intel® LXT9785/LXT9785E Typical RMII Interface Diagram..................................................... 143 26 Intel® LXT9785/LXT9785E Typical RMII Quad Sectionalization Diagram................................ 144 27 Intel® LXT9785/LXT9785E 100BASE-X Frame Format ........................................................... 145 28 Intel® LXT9785/LXT9785E Protocol Sublayers ........................................................................ 146 29 Typical IP Telephone System Connection................................................................................ 152 30 Intel® LXT9785E Negotiation Flow Chart ................................................................................. 156 31 Intel® LXT9785/LXT9785E LED Pulse Stretching .................................................................... 158 32 Intel® LXT9785/LXT9785E RMII Programmable Out-of-Band Signaling.................................. 158 33 LED Circuit ............................................................................................................................... 167 34 Intel® LXT9785/LXT9785E Power and Ground Supply Connections ....................................... 168 35 Intel® LXT9785/LXT9785E Typical Twisted-Pair Interface....................................................... 169 36 Recommended Intel® LXT9785/LXT9785E-to-3.3 V Fiber Transceiver Interface Circuitry ...... 170 37 Recommended Intel® LXT9785/LXT9785E-to-5 V Fiber Transceiver Interface Circuitry ......... 171 38 ON Semiconductor Triple PECL-to-LVPECL Translator .......................................................... 172 |
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