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LT3468-2 Fiches technique(PDF) 6 Page - Linear Technology

No de pièce LT3468-2
Description  Photoflash Capacitor Chargers in ThinSOT
Download  12 Pages
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Fabricant  LINER [Linear Technology]
Site Internet  http://www.linear.com
Logo LINER - Linear Technology

LT3468-2 Fiches technique(HTML) 6 Page - Linear Technology

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LT3468/LT3468-1/LT3468-2
6
sn346812 346812fs
SW (Pin 1): Switch Pin. This is the collector of the internal
NPN Power switch. Minimize the metal trace area con-
nected to this pin to minimize EMI. Tie one side of the
primary of the transformer to this pin. The target output
voltage is set by the turns ratio of the transformer.
Choose Turns Ratio N by the following equation:
N
VOUT
=
+ 2
31 5
.
Where: VOUT is the desired output voltage.
You must tie a Schottky diode from GND to SW, with the
anode at GND for proper operation of the circuit. Please
refer to the applications section for further information.
GND (Pin 2): Ground. Tie directly to local ground plane.
DONE (Pin 3): Open NPN Collector Indication Pin. When
target output voltage is reached, NPN turns on. This pin
needs a pull-up resistor or current source.
CHARGE (Pin 4): Charge Pin. This pin must be brought
high (>1V) to enable the part. A low (<0.3V) to high (>1V)
transition on this pin puts the part into power delivery
mode. Once the target output voltage is reached, the part
will stop charging the output. Toggle this pin to start
charging again. Ground to shut down. You may bring this
pin low during a charge cycle to halt charging at any time.
VIN (Pin 5): Input Supply Pin. Must be locally bypassed
with a good quality ceramic capacitor. Input supply must
be 2.5V or higher.
PI FU CTIO S
BLOCK DIAGRA
VIN
SW
+
DONE
CHARGE
C1
T1
R2
60k
Q1
ENABLE
COUT
PHOTOFLASH
CAPACITOR
36mV
20mV
TO BATTERY
D2
Q2
VOUT
D1
LT3468: RSENSE = 0.015Ω
LT3468-2: RSENSE = 0.022Ω
LT3468-1: RSENSE = 0.03Ω
3486 BD
1
GND
5
3
4
2
+
+
+
+
+–
ONE-
SHOT
ONE-
SHOT
DRIVER
PRIMARY
SECONDARY
MASTER
LATCH
RSENSE
DCM COMPARATOR
VOUT COMPARATOR
R1
2.5k
S
RQ
1.25V
REFERENCE
Q3
Q1
QQ
SR
A3
A1
A2
CHIP ENABLE
Figure 1


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