SM560
Document #: 38-07020 Rev. *E
Page 2 of 8
Functional Description
The Cypress SM560 is a Spread Spectrum Clock Generator
(SSCG) IC used for the purpose of reducing Electro Magnetic
Interference (EMI) found in today’s high-speed digital
electronic systems.
The SM560 uses a Cypress-proprietary Phase-Locked Loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and frequency modulate the input frequency of the
reference clock. By frequency modulating the clock, the
measured EMI at the fundamental and harmonic frequencies
of Clock (SSCLK1) is greatly reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory requirements and time to
market without degrading the system performance.
The SM560 is a very simple and versatile device to use. The
frequency and spread% range is selected by programming S0
and S1digital inputs. These inputs use three (3) logic states
including High (H), Low (L) and Middle (M) logic levels to select
one of the nine available Frequency Modulation and Spread%
ranges. Refer to Table 1 for programming details.
The SM560 is optimized for SVGA (40 MHz) and XVGA (65
MHz) Controller clocks and also suitable for the applications
with the frequency range of 25 to 108 MHz.
A wide range of digitally selectable spread percentages is
made possible by using three-level (High, Low and Middle)
logic at the S0 and S1 digital control inputs.
The output spread (frequency modulation) is symmetrically
centered on the input frequency.
Spread Spectrum Clock Control (SSCC) function enables or
disables the frequency spread and is provided for easy
comparison of system performance during EMI testing.
The SM560 is available in an eight-pin SOIC package with a 0
to 70
°C operating temperature range.
Pin Definitions
Pin
Name
Type
Description
1
Xin/CLK
I
Clock or Crystal connection input. Refer to Table 1 for input frequency range selection.
2
VDD
P
Positive power supply.
3
GND
P
Power supply ground.
4
SSCLK
O
Modulated clock output.
5
SSCC
I
Spread Spectrum Clock Control (Enable/Disable) function. SSCG function is enabled
when input is high and disabled when input is low. This pin is pulled high internally.
6
S1
I
Tri-level Logic input control pin used to select frequency and bandwidth.
Frequency/bandwidth selection and Tri-level Logic programming. See Figure 1.
7
S0
I
Tri-level Logic input control pin used to select frequency and bandwidth.
Frequency/bandwidth selection and Tri-level Logic programming. See Figure 1.
8
Xout
O
Oscillator output pin connected to crystal. Leave this pin unconnected If an external
clock drives Xin/CLK.
Table 1. Frequency and Spread% Selection (Center Spread)
25 – 54 M H z (L o w R a n g e )
Input
Fre q ue n c y
(M H z )
S1= M
S0= M
(% )
S1 = M
S0= 0
(% )
S1= 1
S0= 0
(% )
S1= 0
S0= 0
(% )
S1= 0
S0 = M
(% )
25 – 35
3.8
3.2
2.8
2.3
1.9
35 – 40
3.5
3.0
2.5
2.1
1.7
40 – 45
3.2
2.8
2.4
1.9
1.6
45 – 50
3.0
2.6
2.2
1.8
1.5
50 – 54
2.8
2.4
2.0
1.7
1.4
50 – 108 M H z (H ig h R a n g e )
Input
Fre q ue n c y
(M H z )
S1 = 1
S0= M
(% )
S1= 0
S0= 1
(% )
S1= 1
S0= 1
(% )
S1 = M
S0= 1
(% )
50 – 60
2.5
1.9
1.2
1.0
60 – 70
2.4
1.8
1.1
0.9
70 – 80
2.3
1.6
1.1
0.9
80 – 1 0 0
2.0
1.4
1.0
0.8
100 – 10 8
1.8
1.3
0.8
0.6
S e lec t th e
Freq ue n c y a n d
C e n ter S p read %
de s ire d an d th en
s et S1 , S0 a s
in d ica ted .
S e lec t th e
Freq ue n c y a n d
C e n ter S p read %
de s ire d an d th en
s et S1 , S0 a s
in d ica ted .
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