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NUS5530MN Fiches technique(PDF) 3 Page - ON Semiconductor |
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NUS5530MN Fiches technique(HTML) 3 Page - ON Semiconductor |
3 / 9 page NUS5530MN http://onsemi.com 3 ELECTRICAL CHARACTERISTICS FOR P−CHANNEL FET (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = −250 mA −0.6 −1.2 V Gate−Body Leakage IGSS VDS = 0 V, VGS = "12 V "100 nA Zero Gate Voltage Drain Current IDSS VDS = −16 V, VGS = 0 V −1.0 mA VDS = −16 V, VGS = 0 V, TJ = 85°C −5.0 On−State Drain Current (Note 5) ID(on) VDS v −5.0 V, VGS = −4.5 V −20 A Drain−Source On−State Resistance (Note 5) rDS(on) VGS = −3.6 V, ID = −1.0 A − 0.050 0.06 W VGS = −2.5 V, ID = −1.0 A 0.070 0.083 Forward Transconductance (Note 5) gfs VDS = −10 V, ID = −3.9 A 12 Mhos Diode Forward Voltage (Note 5) VSD IS = −2.1 A, VGS = 0 V −0.8 −1.2 V Dynamic (Note 6) Total Gate Charge QG VDS = −10 V, VGS = −4.5 V, ID = −3.9 A 9.7 22 nC Gate−Source Charge QGS 1.2 Gate−Drain Charge QGD 3.6 Input Capacitance Ciss VDS = −5.0 Vdc, VGS = 0 Vdc, f = 1.0 MHz 710 pF Output Capacitance Coss 400 Reverse Transfer Capacitance Crss 140 Turn−On Delay Time td(on) VDD = −10 V, RL = 10 W ID ^ −1.0 A, VGEN = −4.5 V, RG = 6 W 14 30 ns Rise Time tr 22 55 Turn−Off Delay Time td(off) 42 100 Fall Time tf 35 70 Source−Drain Reverse Recovery Time trr IF = −1.1 A, di/dt = 100 A/ms 30 60 4. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). 5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 6. Guaranteed by design, not subject to production testing. |
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