Preliminary Technical Data

AD7367

Rev. PrD | Page 7 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

2

3

ADDR

4

DGND

24

23

BUSY

22

CNVST

21

RANGE0

5

RANGE1

6

AGND

7

SCLK

20

CS

19

REFSEL

18

8

AGND

17

9

16

10

15

11

14

12

13

AD7367

TOP VIEW

(Not to Scale)

Figure 2 24-Lead RU-24.

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 23

Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out

on the falling edge of the SCLK input and 14 SCLK cycles are required to access the data. The data

simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream

consists of the 14 bits of conversion data and is provided MSB first. If CS is held low for a further 14 SCLK

using only one serial port. See the Serial Interface section.

2

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface will

operate. This pin should be decoupled to DGND. The voltage range on this pin is 2.7V to 5.25V and may be

3

difference between them never exceed 0.3 V even on a transient basis. This supply should be decoupled to

4,5

RANGE0,

RANGE1

Analog Input Range Selection. Logic inputs. The polarity on these pins determines the input range of the

analog input channels. See Analog Inputs section and Table 7 for details

6

ADDR

Multiplexer Select. Logic input. This input is used to select the pair of channels to be simultaneously

converted, either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADCB. The logic

state on this pin is latched on the rising edge of BUSY to set up the multiplexer for the next conversion.

7,17

AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7367. All analog input signals and

any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to

the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and

must not be more than 0.3 V apart, even on a transient basis.

8

transient basis. This supply should be decoupled to AGND. 10 µF and 100 nF decoupling capacitors should

9,16

Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference

buffer for each respective ADC. For best performance it is recommended to use 680nF decoupling capacitor

on these pins. Provided the output is buffered, the on-chip reference can be taken from these pins and