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AD5363BCPZ Fiches technique(PDF) 9 Page - Analog Devices

No de pièce AD5363BCPZ
Description  8-Channel, 16/14-Bit, Serial Input, Voltage-Output DAC
Download  25 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5363BCPZ Fiches technique(HTML) 9 Page - Analog Devices

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Preliminary Technical Data
AD5362/AD5363
Rev. P
rF | Page 9 of 25
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RESET
BIN/2SCOMP
BUSY
GPIO
MON_OUT
MON_IN0
NC
NC
NC
NC
NC
VDD
VSS
VREF1
NC = NO CONNECT
PIN 1
INDICATOR
AD5362/
AD5363
TOP VIEW
(Not to scale)
NC
NC
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
TEMP_OUT
MON_IN1
VREF0
NC
NC
VSS
VDD
5362LFCSP-
060414
39
38
37
36
35
34
33
32
31
30
29
28
27
NC = NO CONNECT
PIN 1
INDICATOR
AD5362/
AD5363
TOP VIEW
(Not to scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
52 51 50 49 48 47 46 45
43 42 41 40
44
LDAC
CLR
RESET
BIN/2SCOMP
BUSY
GPIO
MON_OUT
MON_IN0
NC
NC
VDD
VSS
VREF1
NC
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
TEMP_OUT
MON_IN1
VREF0
NC
VSS
VDD
NC
5362-060414
Figure 6
. 56 Lead LFCSP Pin Configuration
Figure 7
. 52 Lead LQFP Pin Configuration
Table 5. Pin Function Descriptions
Pin Name
Function
DVCC
Logic Power Supply; 2.3 V to 5.5 V. These pins should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors.
VSS
Negative Analog Power Supply; −11.4 V to −16.5 V for specified performance. These pins should be decoupled with 0.1 µF
ceramic capacitors and 10 µF capacitors.
VDD
Positive Analog Power Supply; +11.4 V to +16.5 V for specified performance. These pins should be decoupled with 0.1 µF
ceramic capacitors and 10 µF capacitors.
AGND
Ground for All Analog Circuitry. All AGND pins should be connected to the AGND plane.
DGND
Ground for All Digital Circuitry. All DGND pins should be connected to the DGND plane.
SIGGND0
Reference Ground for DACs 0 to 3. VOUT0 to VOUT3 are referenced to this voltage.
SIGGND1
Reference Ground for DACs 4 to 7. VOUT4 to VOUT7 are referenced to this voltage.
VREF0
Reference Input for DACs 0 to 3. This voltage is referred to AGND.
VREF1
Reference Input for DACs 4 to 7. This voltage is referred to AGND.
VOUT0 to
VOUT15
DAC Outputs. Buffered analog outputs for each of the 16 DAC channels. Each analog output is capable of driving an output
load of 10 kΩ to ground. Typical output impedance of these amplifiers is 0.5 Ω.
SYNC
Active Low or SYNC Input for SPI Interface. This is the frame synchronization signal for the SPI serial interface. See SPI
timing diagrams and descriptions for more details.
SCLK
Serial Clock Input for SPI Interface. See SPI timing diagrams and descriptions for more details.
SDI
Serial Data Input for SPI Interface. See SPI timing diagrams and descriptions for more details.
SDO
Serial Data Output for SPI Interface. See SPI timing diagrams and descriptions for more details.
LDAC
Load DAC Logic Input (Active Low). See the BUSY and LDAC FUNCTIONS section for more information.
BUSY
Digital Input/Open-Drain Output. BUSY is open-drain when an output. See the BUSY and LDAC FUNCTIONS section for
more information
RESET
Asynchronous Digital Reset Input
CLR
Asynchronous clear input (level sensitive, active low). See the Clear Function section for more information
PEC
Packet Error Check output. This is an open-drain output with a 50 k
Ω pullup, that goes low if the packet error check fails.
TEMP_OUT
Provides an output voltage proportional to chip temperature. This is typically 1.5 V at 25 C with an output variation of 5
mV/C.
MON_OUT
Analog multiplexer output. Any DAC output or the MON_IN0 or the MON_IN1 input can be switched to this output.
MON_IN0,
MON_IN1
Analog multiplexer inputs, which can be switched to MON_OUT.


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