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ADN2818ACP-RL Fiches technique(PDF) 11 Page - Analog Devices |
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ADN2818ACP-RL Fiches technique(HTML) 11 Page - Analog Devices |
11 / 35 page Preliminary Technical Data ADN2817/ADN2818 Rev.Pr A | Page 11 of 35 I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION 1 A5 0 000 0 X MSB = 1 SET BY PIN 19 0 = WR 1 = RD SLAVE ADDRESS [6...0] R/W CTRL. Figure 7. Slave Address Configuration S SLAVE ADDR, LSB = 0 (WR) A(S) A(S) A(S) DATA SUB ADDR A(S) P DATA Figure 8. I2C Write Data Transfer S S = START BIT P = STOP BIT A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(M) = LACK OF ACKNOWLEDGE BY MASTER S SLAVE ADDR, LSB = 0 (WR) SLAVE ADDR, LSB = 1 (RD) A(S) A(S) SUB ADDR A(S) DATA A(M) DATA P A(M) Figure 9. I2C Read Data Transfer START BIT S STOP BIT P ACK ACK WR ACK D0 D7 A0 A7 A5 A6 SLADDR[4...0] SLAVE ADDRESS SUB ADDRESS DATA SUB ADDR[6...1] DATA[6...1] SCK SDA Figure 10. I2C Data Transfer Timing tBUF SDA SS P S SCK tF tLOW tR tF tHD;STA tHD;DAT tSU;DAT tHIGH tSU;STA tSU;STO tHD;STA tR Figure 11. I2C Port Timing Diagram |
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