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DTC114EM3T5G Fiches technique(PDF) 1 Page - ON Semiconductor |
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DTC114EM3T5G Fiches technique(HTML) 1 Page - ON Semiconductor |
1 / 10 page © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 3 1 Publication Order Number: DTC114EM3/D DTC114EM3T5G Series Digital Transistors (BRT) NPN Silicon Surface Mount Transistors with Monolithic Bias Resistor Network This new series of digital transistors is designed to replace a single device and its external resistor bias network. The digital transistor contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base−emitter resistor. The digital transistor eliminates these individual components by integrating them into a single device. The use of a digital transistor can reduce both system cost and board space. The device is housed in the SOT−723 package which is designed for low power surface mount applications. Features • Simplifies Circuit Design • Reduces Board Space • Reduces Component Count • The SOT−723 Package can be Soldered using Wave or Reflow. • Available in 4 mm, 8000 Unit Tape & Reel • These are Pb−Free Devices MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Symbol Value Unit Collector-Base Voltage VCBO 50 Vdc Collector-Emitter Voltage VCEO 50 Vdc Collector Current IC 100 mAdc Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. NPN SILICON DIGITAL TRANSISTORS PIN 3 COLLECTOR (OUTPUT) PIN 2 EMITTER (GROUND) PIN 1 BASE (INPUT) R1 R2 xx = Specific Device Code (See Marking Table on page 2) M = Date Code http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ORDERING INFORMATION MARKING DIAGRAM SOT−723 CASE 631AA STYLE 1 3 2 1 xx |
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