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CS51220 Fiches technique(PDF) 9 Page - ON Semiconductor |
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CS51220 Fiches technique(HTML) 9 Page - ON Semiconductor |
9 / 16 page CS51220 http://onsemi.com 9 VCC Power Up and Fault Conditions During power up, an undervoltage lockout comparator monitors VCC and disables VREF, (which in turn disables the entire IC), until the VCC voltage reaches its start threshold. Hysteresis prevents “chattering” caused by the source impedance of the VCC supply. VREF can also be disabled using the Disable input pin, which is active high. An internal pull−down resistor ensures the IC will start up if the Disable pin is allowed to float. In VCC or Disable lockout mode, the output stage is held low by the output pull−down resistance. After VREF turns on, there are three conditions that can cause fault mode: 1. The 3.3 V VREF is below regulation, 2. The OV pin rises above overvoltage threshold, or 3. The UV pin falls below undervoltage threshold. Fault detection will cause the VO output to go low and the SS pin to discharge. The UV and OV inputs are typically used to monitor the input line voltage. The undervoltage comparator has a built−in hysteresis voltage, while the hysteresis for the OV comparator is programmable through a current sourced from the pin when above the threshold, and the equivalent external resistance. The fault condition can only be reset after the SS pin has been completely discharged and all faults have been removed. After a fault is removed or upon initial startup, the SS pin charges at a rate determined by an internal charge current and an external capacitor. The rising voltage on the SS pin will override the regulation feedback voltage on the COMP pin and clamp the duty cycle, helping to reduce any in−rush current during startup. The duration of the Soft Start is typically set with a capacitor from 0.01 μF to 0.1 μF. Overcurrent Protection The CS51220 uses the “soft hiccup” technique to provide an adjustable and predictable overcurrent limit. By choosing external component values the designer can select pulse−by−pulse current limit, soft hiccup current limit or hard hiccup limit. Normal pulse−by−pulse current limit can be obtained by selecting the ISET resistor values for a low Thevenin resistance to the ISET pin. However with normal pulse−by−pulsecurrent limit, the secondary currents during short circuits may be several times the maximum output current. Soft hiccup limit can be obtained by setting the ISET resistor values for a higher thevenin resistance. During overcurrent conditions, the ISET level will fold back, after a short delay, to reduce the pulse by pulse threshold. If desired, the short circuit current can be chosen to be equal to or even less than the maximum output current. During soft hiccup the circuit will periodically disable the foldback and attempt to restart. Hard hiccup limit can be obtained by setting the ISET resistor values so that the ISET pin is held below 200 mV during foldback. During overcurrent conditions, the ISET level will fold back, after a short delay, preventing any gate pulses. When the SS capacitor is completely discharged, the circuit will attempt restart. This configuration provides the lowest power dissipation during short outputs. The circuit functions can be best described by discussing the block diagram and illustrations of expected waveforms. Actual waveforms, values and circuit configurations from a design will be used. The design is from the 5.0 V supply of a dual synchronized converter. The current is monitored with a voltage at the ISENSE pin. The ISENSE signal is slightly attenuated DC shifted by 200 mV, and is compared with the threshold voltage programmed by the voltage at the ISET pin. If the current signal reaches the threshold voltage, the overcurrent comparator resets the VO latch and terminates the VO pulse. The overcurrent comparator has a maximum common mode input voltage of 1.8 V. However, an ISET voltage below 1.0 V is desirable for reducing the comparator’s propagation delay. During initial turnon of the power supply, normal pulse−by−pulse overcurrent control is used to protect the power supply switches. This is accomplished by comparing the voltage at the ISENSE input to the voltage at the ISET pin and using this to limit the duty factor of VO, the gate drive signal. This current limit control is maintained until the SS voltage reaches 2.9 V. |
Numéro de pièce similaire - CS51220 |
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Description similaire - CS51220 |
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