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AD5062 Fiches technique(PDF) 4 Page - Analog Devices

No de pièce AD5062
Description  Full Accurate 16 Bit Vout nanoDac, 2.7V- 5.5V, in a Sot 23
Download  17 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

AD5062 Fiches technique(HTML) 4 Page - Analog Devices

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AD5062/AD5063
Preliminary Technical Data
Rev. Pr B | Page 4 of 17
TIMING CHARACTERISTICS
(VDD = 2.7-5.5 V; all specifications TMIN to TMAX unless otherwise noted)
Parameter
Limit1
Unit
Test Conditions/Comments
t1
3
33
ns min
SCLK Cycle Time
t2
13
ns min
SCLK High Time
t3
12
ns min
SCLK Low Time
t4
13
ns min
SYNC to SCLK Falling Edge Setup Time
t5
5
ns min
Data Setup Time
t6
4.5
ns min
Data Hold Time
t7
0
ns min
SCLK Falling Edge to
SYNC Rising Edge
t8
33
ns min
Minimum
SYNC High Time
t9
13
ns min
SYNC Rising Edge to next SCLK Fall
Ignore
.
NOTES
1All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2See Figure 1.
3Maximum SCLK frequency is 30 MHz.
Specifications subject to change without notice.
Figure 1. Timing Diagram


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