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SC18IS600 Fiches technique(PDF) 1 Page - NXP Semiconductors

No de pièce SC18IS600
Description  SPI to IC-bus interface
Download  28 Pages
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SC18IS600 Fiches technique(HTML) 1 Page - NXP Semiconductors

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1.
General description
The SC18IS600/601 is designed to serve as an interface between the standard SPI of a
host (microcontroller, microprocessor, chip set, etc.) and the serial I2C-bus. This allows
the host to communicate directly with other I2C-bus devices. The SC18IS600/601 can
operate as an I2C-bus master-transmitter or master-receiver. The SC18IS600/601
controls all the I2C-bus specific sequences, protocol, arbitration and timing.
The key distinction between the SC18IS600 and the SC18IS601 lies in the clock source:
internal (SC18IS600) versus external (SC18IS601).
2.
Features
I SPI slave interface
I SPI Mode 3
I Master I2C-bus controller
I General Purpose Input/Output (GPIO) pins: 4 (SC18IS600); 3 (SC18IS601)
I Two quasi-bidirectional I/O pins
I 5 V tolerant I/O pins
I High-speed SPI:
N Up to 3 Mbit/s (SC18IS601)
N Up to 1.2 Mbit/s (SC18IS600)
I High-speed I2C-bus: 400 kbit/s
I 96-byte transmit buffer
I 96-byte receive buffer
I 2.4 V to 3.6 V operation
I Power-down mode with WAKEUP pin
I Oscillator: internal (SC18IS600); external (SC18IS601)
I Active LOW interrupt output
I Available in very small TSSOP16 package
3.
Ordering information
SC18IS600/601
SPI to I2C-bus interface
Rev. 03 — 13 December 2006
Product data sheet
Table 1.
Ordering information
Type number
Package
Name
Description
Version
SC18IS600IPW
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
SC18IS601IPW


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