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SC18IS600 Fiches technique(PDF) 8 Page - NXP Semiconductors

No de pièce SC18IS600
Description  SPI to IC-bus interface
Download  28 Pages
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Fabricant  PHILIPS [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SC18IS600 Fiches technique(HTML) 8 Page - NXP Semiconductors

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SC18IS600_601_3
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 December 2006
8 of 28
NXP Semiconductors
SC18IS600/601
SPI to I2C-bus interface
6.2.2 I/O pins state register (IOState)
When read, this register returns the actual state of all programmable and
quasi-bidirectional I/O pins. When written, each register bit will be transferred to the
corresponding I/O pin programmed as output.
6.2.3 I2C-bus address register (I2CAdr)
The contents of the register represents the device’s own I2C-bus address. The most
significant bit corresponds to the first bit received from the I2C-bus after a START
condition. The least significant bit is not used, but should be programmed with a ‘0’.
I2CAdr is not needed for device operation, but should be configured so that its address
does not conflict with an I2C-bus device address used by the bus master.
6.2.4 I2C-bus clock rates register (I2CClk)
This register determines the I2C-bus clock frequency. Various clock rates are shown in
Table 6 for the SC18IS600. The frequency can be determined using the following formula:
Fig 8.
Push-pull output configuration
002aab885
strong
VDD
P
VSS
pin latch data
GPIO pin
glitch rejection
input data
N
Table 5.
IOState - I/O pins state register (address 0x01) bit description
Bit
Symbol
Description
7:6
-
reserved
5
IO5
Set the logic level on the output pins.
Write to this register:
logic 0 = set output pin to zero
logic 1 = set output pin to one
A read from this register returns states of all pins.
4
IO4
3
GPIO3 (SC18IS600 only)
2
GPIO2
1
GPIO1
0
GPIO0
I
2
C-bus clock frequency
7.3728
10
6
×
4
I 2CClk
×
------------------------------- Hz
()
=


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